View STLC5466_67017.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

STLC5466
64 CHANNEL-MULTI HDLC WITH N X 64KB/S SWITCHING MATRIX ASSOCIATED
PRELIMINARY DATA
s
s
s
s
s
s
s
s
s
s s
s
s
s s
s s
64 TX HDLCs with broadcasting capability and/ or CSMA/CR function with automatic restart in case of Tx frame abort 64 RX HDLCs including Address Recognition 16 Command/Indicate Channels (4 or 6-bit primitive) 16 Monitor Channels processed in accordance with GCI or V* 256 x 256 Switching Matrix without blocking and with Time Slot Sequence Integrity and loopback per bidirectional connection DMA Controller for 64 Tx Channels and 64 Rx Channels HDLCs AND DMA CONTROLLER ARE CAPABLE OF HANDLING A MIX OF LAPD,LAPB, SS7, CAS AND PROPRIETARY SIGNALLINGS External shared memory access between DMA Controller and Micro processor SINGLE MEMORY SHARED BETWEEN n x MULTI-HDLCs AND SINGLE MICRO PROCESSOR ALLOWS TO HANDLE n x 64 CHANNELS Bus Arbitration Interface for various 8,16 or 32 bit Microprocessors with fetch memory to accelerate the exchanges between Microprocessor and SHARED MEMORY SDRAM Controller allows to inter face up to 16 Megabytes of Synchronous Dynamic RAM Interrupt Controller to store automatically events in shared memory Boundary scan for test facility TQFP176 package 24 x 24 x 1.40 #MS-026BGA HCMOS6; 0.35 micron; 3.3volts +/-5% Operating temperature: -40 to +85 /C
DESCRIPTION The STLC5466 is a Subscriber line interface card controller for Central Office, Central Exchange, NT2 and PBX capable of handling:
s s s s
16 U Interfaces or 2 Megabits line interface cards or 16 SLICs (Plain Old Telephone Service) or Mixed analogue and digital Interfaces (SLICs or U Interfaces) or 16 S Interfaces Switching Network with centralized processing.
s s
TQFP176 (Plastic Quad Flat Pack) ORDERING NUMBER: STLC5466
November 1999
This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice.
1/130
STLC5466
TABLE OF CONTENTS I I.1 I.2 I.3 I.3.1 I.3.2 I.3.3 II III III.1 III.1.1 III.1.2 III.1.3 III.1.4 III.1.5 III.1.5.1 III.1.5.2 III.1.6 III.1.6.1 III.1.6.2 III.1.6.3 III.1.7 III.1.8 III.2 III.2.1 III.2.1.1 III.2.1.2 III.2.1.3 III.2.2 III.2.3 III.2.4 III.2.4.1 III.2.4.2 III.2.4.3 III.2.5 III.2.6 III.2.6.1 III.2.6.2 III.3 III.3.1 III.3.2 PIN INFORMATION................................................................................................................6 PIN CONNECTIONS ..............................................................................................................6 PIN DESCRIPTION ................................................................. ..............................................7 PIN DEFINITION...................................................................... ............................................12 Input Pin Definition................................................................................................................12 Output Pin Definition ............................................................................................................12 Input/Output Pin Definition. ..................................................................................................12 BLOCK DIAGRAM ...............................................................................................................13 FUNCTIONAL DESCRIPTION .............................................................................................13 THE SWITCHING MATRIX N X 64 KBITS/S........................................................................13 Function Description .............................................................................................................13 Architecture of the Matrix .....................................................................................................13 Connection Function ............................................................................................................13 Loop Back Function .............................................................................................................15 Delay through the Matrix ......................................................................................................15 Variable Delay Mode ........................................................................................................15 Sequence Integrity Mode ..................................................................................................15 Connection Memory .............................................................................................................15 Description .......................................................................................................................15 Access to Connection Memory .........................................................................................15 Access to Data Memory....................................................................................................15 Switching at 32 Kbit/s ...........................................................................................................15 Switching at 16 Kbit/s ...........................................................................................................16 HDLC CONTROLLER.............................................................. ............................................16 Function description .............................................................................................................16 Format of the HDLC Frame ..............................................................................................16 Composition of an HDLC Frame .......................................................................................16 Description and Functions of the HDLC Bytes..................................................................16 CSMA/CR Capability ............................................................................................................17 Time Slot Assigner Memory .................................................................................................17 Data Storage Structure .........................................................................................................18 Reception..........................................................................................................................18 Transmission.....................................................................................................................18 Frame Relay .....................................................................................................................18 Transparent Modes ..............................................................................................................18 Command of the HDLC Channels ........................................................................................19 Reception Control .............................................................................................................19 Transmission Control ........................................................................................................19 C/I AND MONITOR.................................................................. ............................................19 Function Description ............................................................................................................19 GCI and V* Protocol .............................................................................................................19
2/130
STLC5466
III.3.3 III.3.4 III.3.5 III.4 III.5 III.6 III.6.1 III.6.2 III.6.2.1 III.6.2.2 III.6.2.3 III.7 III.7.1 III.7.2 III.7.3 III.7.4 III.7.4.1 III.7.4.2 III.7.4.3 III.7.4.4 III.8 III.9 III.9.1 III.9.2 III.10 III.10.1 III.10.2 III.10.3 III.10.4 III.10.5 III.11 III.12 III.13 IV V VI VI.1 VI.2 VI.3 Structure of the Treatment ...................................................................................................20 CI and Monitor Channel Configuration..................................................................................20 CI and Monitor Transmission/Reception Command .............................................................20 SCRAMBLER AND DESCRAMBLER...................................... ............................................20 CONNECTION BETWEEN "ISDN CHANNELS" AND GCI CHANNELS ..............................20 MICROPROCESSOR INTERFACE......................................... ............................................21 Description ...........................................................................................................................21 Buffer ...................................................................................................................................21 Write FIFO ........................................................................................................................21 Read Fetch Memory .........................................................................................................23 Definition of the Interface for the different microprocessors..............................................23 MEMORY INTERFACE ........................................................... ............................................23 Function Description ............................................................................................................23 Choice of memory versus microprocessor and capacity required ........................................23 Memory Cycle .......................................................................................................................23 Memories composed of different circuits ..............................................................................23 Memory obtained with 1M x16 SDRAM circuit..................................................................23 Memory obtained with 2M x 8 SDRAM circuit...................................................................23 Memory obtained with 8M x 8 SDRAM circuit...................................................................23 Memory obtained with 4M x 16 SDRAM circuit.................................................................24 BUS ARBITRATION ................................................................ ............................................24 CLOCKS .................................................................................. ............................................24 Clock Distribution Selection and Supervision .......................................................................24 VCXO Frequency Synchronization .......................................................................................24 INTERRUPT CONTROLLER................................................... ............................................25 Description ........................................................................................................... ................25 Operating Interrupts (INT0 Pin)........................................................................................ .....25 Time Base Interrupts (INT1 Pin) ........................................................................................ ...25 Emergency Interrupts (WDO Pin) ......................................................................................... 25 Interrupt Queues ..................................................................................................................25 WATCHDOG............................................................................ ............................................25 RESET ..................................................................................... ............................................25 BOUNDARY SCAN.................................................................. ............................................26 DC SPECIFICATIONS..........................................................................................................27 LIST OF REGISTERS ..........................................................................................................29 INTERNAL REGISTERS ......................................................................................................31 IDENTIFICATION AND DYNAMIC COMMAND REGISTER... IDCR (00)H .........................31 GENERAL CONFIGURATION REGISTER 1 .......................... GCR1 (02)H........................31 INPUT MULTIPLEX CONFIGURATION REGISTER 0............ IMCR0 (04)H.......................33
3/130
STLC5466
VI.4 VI.5 VI.6 VI.7 VI.8 VI.9 VI.10 VI.11 VI.12 VI.13 VI.14 VI.15 VI.16 VI.17 VI.18 VI.19 VI.20 VI.21 VI.22 VI.23 VI.24 VI.25 VI.26 VI.27 VI.28 VI.29 VI.30 VI.31 VI.32 VI.33 VI.34 VI.35 VI.36 VI.37
4/130
INPUT MULTIPLEX CONFIGURATION REGISTER 1 ........... IMCR1 (06)H.......................34 OUTPUT MULTIPLEX CONFIGURATION REGISTER 0........ OMCR0 (08)H.....................34 OUTPUT MULTIPLEX CONFIGURATION REGISTER 1........ OMCR1 (0A)H ....................34 SWITCHING MATRIX CONFIGURATION REGISTER ........... SMCR (0C)H.......................35 CONNECTION MEMORY DATA REGISTER ......................... CMDR (0E)H.......................37 CONNECTION MEMORY ADDRESS REGISTER ................. CMAR (10)H .......................41 SEQUENCE FAULT COUNTER REGISTER ......................... SFCR (12)H ........................45 TIME SLOT ASSIGNER ADDRESS REGISTER 1.................. TAAR1 (14)H ......................45 TIME SLOT ASSIGNER DATA REGISTER 1 ......................... TADR1 (16)H ......................45 HDLC TRANSMIT COMMAND REGISTER 1 ......................... HTCR1 (18)H......................46 HDLC RECEIVE COMMAND REGISTER 1 ............................ HRCR1 (1A)H .....................48 ADDRESS FIELD RECOGNITION ADDRESS REGISTER 1 . AFRAR1 (1C)H ...................50 ADDRESS FIELD RECOGNITION DATA REGISTER 1 ......... AFRDR1 (1E)H ...................50 FILL CHARACTER REGISTER 1 ............................................ FCR1 (20)H ........................51 GCI CHANNELS DEFINITION REGISTER 0 ......................... GCIR0 (22)H.......................51 GCI CHANNELS DEFINITION REGISTER 1 .......................... GCIR1 (24)H.......................51 GCI CHANNELS DEFINITION REGISTER 2 .......................... GCIR2 (26)H.......................52 GCI CHANNELS DEFINITION REGISTER 3 .......................... GCIR3 (28)H.......................52 TRANSMIT COMMAND / INDICATE REGISTER .................. TCIR (2A)H .........................52 TRANSMIT MONITOR ADDRESS REGISTER....................... TMAR (2C)H .......................53 TRANSMIT MONITOR DATA REGISTER .............................. TMDR (2E)H .......................54 TRANSMIT MONITOR INTERRUPT REGISTER.................... TMIR (30)H .........................55 MEMORY INTERFACE CONFIGURATION REGISTER ......... MICR (32)H.........................55 INITIATE BLOCK ADDRESS REGISTER 1 ........................... IBAR1 (34)H .......................56 INTERRUPT QUEUE SIZE REGISTER ................................. IQSR (36)H .........................56 INTERRUPT REGISTER ........................................................ IR (38)H ..............................57 INTERRUPT MASK REGISTER.............................................. IMR (3A)H...........................58 TIMER REGISTER 1 ............................................................... TIMR1 (3C)H ......................59 TEST REGISTER .................................................................... TR (3E)H.............................59 GENERAL CONFIGURATION REGISTER 2 .......................... GCR2 (42)H........................60 SPLIT FETCH MEMORY REGISTER ..................................... SFMR (4E)H .......................61 TIME SLOT ASSIGNER ADDRESS REGISTER 2.................. TAAR2 (54)H ......................62 TIME SLOT ASSIGNER DATA REGISTER 2 ......................... TADR2 (56)H ......................62 HDLC TRANSMIT COMMAND REGISTER 2 ........................ HTCR2 (58)H......................63
STLC5466
VI.38 VI.39 VI.40 VI.41 VI.42 VI.43 VI.44 VII VII.1 VII.2 VII.2.1 VII.2.2 VII.2.3 VII.3 VII.3.1 VII.3.2 VII.3.3 VII.4 VII.5 VII.5.1 VII.5.2 VII.6 VII.6.1 VII.6.2 VIII IX HDLC RECEIVE COMMAND REGISTER 2 ........................... HRCR2 (5A)H .....................65 ADDRESS FIELD RECOGNITION ADDRESS REGISTER 2 AFRAR2 (5C)H ...................67 ADDRESS FIELD RECOGNITION DATA REGISTER 2 ......... AFRDR2 (5E)H ...................67 FILL CHARACTER REGISTER 2 ........................................... FCR2 (60)H ........................68 SDRAM MODE REGISTER..................................................... SDRAMR (72)H ..................68 INITIATE BLOCK ADDRESS REGISTER 2 ........................... IBAR2 (74)H .......................69 TIMER REGISTER 2 ............................................................... TIMR2 (7C)H ......................70 EXTERNAL REGISTERS.....................................................................................................71 INITIALIZATION BLOCK IN EXTERNAL MEMORY (IBA1 AND IBA2) RECEIVE DESCRIPTOR......................................................... 71 72
Bits written by the Microprocessor only ...............................................................................72 Bits written by the Rx DMAC only ........................................................................................72 Receive Buffer .....................................................................................................................73 TRANSMIT DESCRIPTOR ...................................................... ............................................73 Bits written by the Microprocessor only ...............................................................................73 Bits written by the Tx DMAC only ........................................................................................74 Transmit Buffer ....................................................................................................................74 RECEIVE & TRANSMIT HDLC FRAME INTERRUPT ............ ............................................75 RECEIVE COMMAND / INDICATE INTERRUPT.................... ............................................76 Receive Command / Indicate Interrupt when TSV = 0 .........................................................76 Receive Command / Indicate Interrupt when TSV = 1 .........................................................77 RECEIVE MONITOR INTERRUPT.......................................... ............................................77 Receive Monitor Interrupt when TSV = 0 .............................................................................77 Receive Monitor Interrupt when TSV = 1 .............................................................................78 TQFP176 PACKAGE MECHANICAL DATA .......................................................................79 FIGURES AND TIMING........................................................................................................80
5/130
6/130
I.1 - Pin Connections
I - PIN INFORMATION
STLC5466
N.C VSS12 TMS TDI TDO TCK VDD3 VSS3 NCS0 NCS1 INT0 INT1 SIZE0/NLDS/NLBA SIZE1/NBHE/NUDS NDSACK0/NDTACK NDSACK1/READY NAS/ALE R/W / NWR NDS/NRD/CLKOUT MOD0 MOD1 MOD2 VDD4 VSS4 A0/AD0 A1/AD1 A2/AD2 A3/AD3 A4/AD4 A5/AD5 A6/AD6 A7/AD7 A8/AD8 A9/AD9 VDD5 VSS5 A10/AD10 A11/AD11 A12/AD12 A13/AD13 A14/AD14 A15/AD15 VDD13 N.C
45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 NREADY 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 176 175 174 173 172 171 170 169 168 167 166 165 164 163 162 161 160 159 158 157 156 155 154 153 152 151 150 149 148 147 146 145 144 143 142 141 140 139 138 137 136 135 134 133 N.C VDD15 NTEST VSS11 VDD11 DM15 DM14 DM13 DM12 DM11 DM10 DM9 DM8 DM7 DM6 DM5 VSS10 VDD10 DM4 DM3 DM2 DM1 DM0 DIN9 SCANM NCAS ADM11 ADM10 VSS9 VDD9 ADM9 ADM8 ADM7 ADM6 ADM5 ADM4 ADM3 ADM2 ADM1 ADM0 VSS8 VDD8 VSS14 N.C N.C VSS15 NRESET MCLK SFS WDO CB1 EC1 VCXO IN VCXO OUT DCLK CLOCKA CLOCKB FRAMEA FRAMEB VDD1 VSS1 FS FSCG FSCV PSS DIN0 DIN1 DIN2 DIN3 DIN4 DIN5 DIN6 DIN7 DIN8 VDD2 VSS2 DOUT0 DOUT1 DOUT2 DOUT3 DOUT4 DOUT5 DOUT6 DOUT7 NDIS/NCS2 NTRST VDD12 N.C
STLC5466
N.C VDD14 EC2 NCE3/ADM13 CB2 NCE2/ADM12 UDQM NCE1 LDQM NCE0 NRAS NWE TRO TRI VSS7 VDD7 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 VSS6 VDD6 A23 A22 A21 A20 A19 A18 A17 A16 VSS13 N.C 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89
STLC5466
I.2 - Pin Description
Pin N Symbol Type Function
30 POWER PINS (all the power and ground pins must be connected) 16 17 31 32 51 52 67 68 79 80 99 100 117 118 135 136 147 148 159 160 172 173 43 46 87 90 131 134 175 2 CLOCKS 4 5 MCLK SFS I3_ft O3_ft Master clock. This input can receive an external clock at 66, 50 or 33MHz. Superframe Synchronisation. Programmable signal from 250 microseconds to 15 seconds. VDD1 VSS1 VDD2 VSS2 VDD3 VSS3 VDD4 VSS4 VDD5 VSS5 VDD6 VSS6 VDD7 VSS7 VDD8 VSS8 VDD9 VSS9 VDD10 VSS10 VDD11 VSS11 VDD12 VSS12 VDD13 VSS13 VDD14 VSS14 VDD15 VSS15 Power Ground Power Ground Power Ground Power Ground Power Ground Power Ground Power Ground Power Ground Power Ground Power Ground Power Ground Power Ground Power Ground Power Ground Power Ground DC supply DC ground DC supply DC ground DC supply DC ground DC supply DC ground DC supply DC ground DC supply DC ground DC supply DC ground DC supply DC ground DC supply DC ground DC supply DC ground DC supply DC ground DC supply DC ground DC supply DC ground DC supply DC ground DC supply DC ground
Type TTL TTL TTL TTL CMOS CMOS
ft: five volts tolerant I1_ft = Input TTL
fnt: five volts not tolerant I2_ft = I1_ft+pull up I3_ft = I1_ft+hysteresis I4_ft = I3_ft+pull up I5_ft = I3_ft+pull down; O6_ft = Output TTL 6mA O6DT_ft = Output TTL 6mA, Open Drain or Tristate O8T_fnt = Output CMOS 8mA I/O8_fnt = Input TTL, /Output CMOS 8mA
I/O6 _ft = Input TTL/ Output TTL 6 mA O3 _ft = Output TTL 3 mA O3T_ft = O3_ft+Tristate O6D_ft = Output TTL 6mA, Open Drain I/O8_fnt = Input TTL, /Output CMOS 8mA; O4_fnt = Output CMOS 4mA
7/130
STLC5466
Pin N 9 10 12 13 14 15 11 Symbol VCXO IN VCXO OUT CLOCKA CLOCKB FRAMEA FRAMEB DCLK Type I3_ft O3_ft I3_ft I3_ft I3_ft I3_ft O6_ft Function VCXO input signal. This signal is compared to clock A(orB) selected inside the Multi-HDLC. VCXO error signal. This pin delivers the result of the comparison. Input Clock A (4096kHz or 8192kHz) Input Clock B (4096kHz or 8192kHz) Clock A at 8kHz Clock B at 8kHz Data Clock issued from Input Clock A (or B). This clock is delivered by the circuit at 4096kHz (or 2048kHz). DOUT0/7 are transmitted on the rising edge of this signal. DIN0/7 are sampled on the falling edge of this signal. Frame synchronization for GCI at 8kHz. This clock is issued from FRAME A (or B). Frame synchronization for V Star at 8kHz Frame synchronization. This signal synchronizes DIN0/8 and DOUT0/7 and CB. Programmable synchronization Signal. PSS is programmed by the PS bit of connection memory.
19 20 18 21
FSCG FSCV* FS PSS
O6_ft O6_ft I3_ft O3_ft
TIME DIVISION MULTIPLEXES (TDM) 22 23 24 25 26 27 28 29 30 153 33 34 35 36 37 38 39 40
Type TTL TTL TTL TTL CMOS CMOS
DIN0 DIN1 DIN2 DIN3 DIN4 DIN5 DIN6 DIN7 DIN8 DIN9 DOUT0 DOUT1 DOUT2 DOUT3 DOUT4 DOUT5 DOUT6 DOUT7
ft: five volts tolerant
I3_ft I3_ft I3_ft I3_ft I3_ft I3_ft I3_ft I3_ft I3_ft I3_ft
TDM0 Data Input 0 TDM1 Data Input 1 TDM2 Data Input 2 TDM3 Data Input 3 TDM4 Data Input 4 TDM5 Data Input 5 TDM6 Data Input 6 TDM7 Data Input 7 TDM8 Data Input 8, Direct access to 1st 32 HDLC Controller TDM9 Data Input 9, Direct access to 2nd 32 HDLC Controller
O6DT_ft TDM0 Data Output 0 O6DT_ft TDM1 Data Output 1 O6DT_ft TDM2 Data Output 2 O6DT_ft TDM3 Data Output 3 O6DT_ft TDM4 Data Output 4 O6DT_ft TDM5 Data Output5 O6DT_ft TDM6 Data Output6 O6DT_ft TDM7 Data Output 7
fnt: five volts not tolerant I3_ft = I1_ft+hysteresis O6_ft = Output TTL 6mA O6DT_ft = Output TTL 6mA, Open Drain or Tristate O8T_fnt = Output CMOS 8mA I/O8_fnt = Input TTL, /Output CMOS 8mA I4_ft = I3_ft+pull up I5_ft = I3_ft+pull down;
I1_ft = Input TTL I2_ft = I1_ft+pull up I/O6 _ft = Input TTL/ Output TTL 6 mA O3 _ft = Output TTL 3 mA O3T_ft = O3_ft+Tristate O6D_ft = Output TTL 6mA, Open Drain I/O8_fnt = Input TTL, /Output CMOS 8mA; O4_fnt = Output CMOS 4mA
8/130
STLC5466
Pin N 41 Symbol NDIS/NCS2 Type I3_ft Function If 386EX interface is not selected: DOUT 0/7 Not Disable. When this pin is at 0V, the Data Output 0/7 are at high impedance. Wired at VDD if not used. If 386EX interface is selected: NCS2 (Chip Select 2) equivalent to NCS1. Chip Select 2: external memory is selected During Chip select (NCS2=0), the output Ready (pin 59) is low impedance and outside Chip select (NCS2=1), the output Ready is high impedance. Contention Bus (CSMA/CR) for 1st 32 HDLC Controller Echo for 1st 32 HDLC Controller. Wired at VSS if not used. Contention Bus (CSMA/CR) for 2nd 32 HDLC Controller Echo for 2nd 32 HDLC Controller. Wired at VSS if not used.
7 8 128 130
CB1 EC1 CB2 EC2
O6D_ft I3_ft O6D_ft I3_ft
BOUDARY SCAN 42 47 48 49 50 NTRST TMS TDI TDO TCK I4_ft I2_ft I2_ft O3T_ft I4_ft Reset for boundary scan Mode Selection for boundary scan Input Data for boundary scan Output Data for boundary scan Clock for boundary scan
MICROPROCESSOR INTERFACE 64 65 66 3 53 54 MOD0 MOD1 MOD2 NRESET NCS0 NCS1 I1_ft I1_ft I1_ft I3_ft I3_ft I3_ft 1 1 0 Circuit Reset Chip Select 0: internal registers are selected Chip Select 1: external memory is selected During Chip select (NCS1=0), the output Ready (pin 59) is low impedance and outside Chip select (NCS1=1), the output Ready is high impedance. Interrupt generated by HDLC, RxC/I or RxMON. Active high. Interrupt1.This pin goes to 5V when the selected clock A (or B) has disappeared; 250s after reset this pin goes to 5V also if clock A is not present. Watch Dog Output.This pin goes to 5V during 250s when the microprocessor has not reset the Watch Dog during the programmable time. Transfer Size0 (68020)/Lower Data Stobe/Local Bus Access# when 386EX Transfer Size1(68020)/Bus High Enable (Intel) / Upper Data Strobe (68000) Data Strobe, Acknowledge and Size0 (68020)/ Data Transfer Acknowledge (68000 and ST10)/ READY# (386EX) Data Strobe, Acknowledge and Size1 (68020)/ Data Transfer Acknowledge (Intel) Address Strobe(Motorola) / Address Latch Enable(Intel) / Address Status 386EX Read/Write (Motorola) / Write(Intel) 1 1 1 0 0 1 0 0 0 68020 1 0 0 ST9 1 0 1 ST10 m 0 1 1 ST10Nm 0 1 0 386EX
80C188 80C186 68000
55 56 6 57 58 59
INT0 INT1 WDO SIZE0/NLDS/NLBA SIZE1/NBHE/NUDS NDSACK0/ NDTACK/ NREADY NDSACK1/ READY NAS/ ALE/NADS R/W / NWR
ft: five volts tolerant I1_ft = Input TTL
O3_ft O3_ft O3_ft I3_ft I3_ft O6T_ft/ O6T_ft/ O6D_ft O6T_ft O6T_ft I3_ft I3_ft
60 61 62
Type TTL TTL TTL TTL CMOS CMOS
fnt: five volts not tolerant I2_ft = I1_ft+pull up I3_ft = I1_ft+hysteresis I4_ft = I3_ft+pull up I5_ft = I3_ft+pull down; O6_ft = Output TTL 6mA O6DT_ft = Output TTL 6mA, Open Drain or Tristate O8T_fnt = Output CMOS 8mA I/O8_fnt = Input TTL, /Output CMOS 8mA
I/O6 _ft = Input TTL/ Output TTL 6 mA O3 _ft = Output TTL 3 mA O3T_ft = O3_ft+Tristate O6D_ft = Output TTL 6mA, Open Drain I/O8_fnt = Input TTL, /Output CMOS 8mA; O4_fnt = Output CMOS 4mA
9/130
STLC5466
Pin N 63 69 70 71 72 73 74 75 76 77 78 81 82 83 84 85 86 91 92 93 94 95 96 97 98 101 102 103 104 105 106 107 108 109 110 111
Type TTL TTL TTL TTL CMOS CMOS
Symbol NDS/ NRD/CLKOUT A0/AD0 A1/AD1 A2/AD2 A3/AD3 A4/AD4 A5/AD5 A6/AD6 A7/AD7 A8/AD8 A9/AD9 A10/AD10 A11/AD11 A12/AD12 A13/AD13 A14/AD14 A15/AD15 A16 A17 A18 A19 A20 A21 A22 A23 DO D1 D2 D3 D4 D5 D6 D7 D8 D9 D10
ft: five volts tolerant I1_ft = Input TTL
Type I3_ft I/O6_ft I/O6_ft I/O6_ft I/O6_ft I/O6_ft I/O6_ft I/O6_ft I/O6_ft I/O6_ft I/O6_ft I/O6_ft I/O6_ft I/O6_ft I/O6_ft I/O6_ft I/O6_ft I1_ft I1_ft I1_ft I1_ft I1_ft I1_ft I1_ft I1_ft I/O6_ft I/O6_ft I/O6_ft I/O6_ft I/O6_ft I/O6_ft I/O6_ft I/O6_ft I/O6_ft I/O6_ft I/O6_ft
Function Data Strobe (Motorola) External resistor at Vss if 68000/ Read Data (Intel)/CLKOUT if 386EX Address bit 0 (Motorola) / Address/Data bit 0 (Intel) Address bit 1 (Motorola) / Address/Data bit 1 (Intel) Address bit 2 (Motorola) / Address/Data bit 2 (Intel) Address bit 3 (Motorola) / Address/Data bit 3 (Intel) Address bit 4 (Motorola) / Address/Data bit 4 (Intel) Address bit 5 (Motorola) / Address/Data bit 5 (Intel) Address bit 6 (Motorola) / Address/Data bit 6 (Intel) Address bit 7 (Motorola) / Address/Data bit 7 (Intel) Address bit 8 (Motorola) / Address/Data bit 8 (Intel) Address bit 9 (Motorola) / Address/Data bit 9 (Intel) Address bit 10 (Motorola) / Address/Data bit 10 (Intel) Address bit 11 (Motorola) / Address/Data bit 11 (Intel) Address bit 12 (Motorola) / Address/Data bit 12 (Intel) Address bit 13 (Motorola) / Address/Data bit 13 (Intel) Address bit14 (Motorola) / Address/Data bit 14 (Intel) Address bit15 (Motorola) / Address/Data bit 15 (Intel) Address bit16 from P Address bit17 from P Address bit18 from P Address bit19 from P Address bit 20 from P Address bit 21 from P Address bit 22 from P Address bit 23 from P Data bit 0 for P if not multiplexed (see Note 1). Data bit 1 for P if not multiplexed Data bit 2 for P if not multiplexed Data bit 3 for P if not multiplexed Data bit 4 for P if not multiplexed Data bit 5 for P if not multiplexed Data bit 6 for P if not multiplexed Data bit 7 for P if not multiplexed Data bit 8 for P if not multiplexed Data bit 9 for P if not multiplexed Data bit 10 for P if not multiplexed
fnt: five volts not tolerant I2_ft = I1_ft+pull up O3T_ft = O3_ft+Tristate
I3_ft = I1_ft+hysteresis O6_ft = Output TTL 6mA
I4_ft = I3_ft+pull up I5_ft = I3_ft+pull down;
I/O6 _ft = Input TTL/ Output TTL 6 mA O3 _ft = Output TTL 3 mA O6D_ft = Output TTL 6mA, Open Drain I/O8_fnt = Input TTL, /Output CMOS 8mA; O4_fnt = Output CMOS 4mA
O6DT_ft = Output TTL 6mA, Open Drain or Tristate O8T_fnt = Output CMOS 8mA I/O8_fnt = Input TTL, /Output CMOS 8mA
10/130
STLC5466
Pin N 112 113 114 115 116 Symbol D11 D12 D13 D14 D15 Type I/O6_ft I/O6_ft I/O6_ft I/O6_ft I/O6_ft Function Data bit 11 for P if not multiplexed Data bit 12 for P if not multiplexed Data bit 13 for P if not multiplexed Data bit 14 for P if not multiplexed Data bit 15 for P if not multiplexed
MEMORY INTERFACE 119 120 121 122 123 124 125 126 127 129 137 138 139 140 141 142 143 144 145 146 149 150 151 152 154 155 156 157 158 161
Type TTL TTL TTL TTL CMOS CMOS
TRI TRO NWE NRAS NCE0 LDQM NCE1 UDQM NCE2/ ADM12 NCE3/ADM13 ADM0 ADM1 ADM2 ADM3 ADM4 ADM5 ADM6 ADM7 ADM8 ADM9 ADM10 ADM11 NCAS SCANM DM0 DM1 DM2 DM3 DM4 DM5
ft: five volts tolerant I1_ft = Input TTL O3 _ft = Output TTL 3 mA
I3_ft O4_fnt
Token Ring Input (for use Multi-HDLCs in cascade) Token Ring Output (for use Multi-HDLCs in cascade)
O8T_fnt Write Enable for SDRAM O8T_fnt Row Address Strobe for SDRAM O8T_fnt Chip Select 0 for SDRAM O8T_fnt Lower Data inputs/outputs mask enable for SDRAM O8T_fnt Chip Select 1 for SDRAM O8T_fnt Upper Data inputs/outputs mask enable for SDRAM O8T_fnt Chip Select 2 for SDRAM/ Address bit 12 for 8Mx8 SDRAM circuit O8T_fnt Chip Select 3 for SDRAM/Address bit 13 for 8Mx8 SDRAM circuit O8T_fnt Address bit 0 for SDRAM O8T_fnt Address bit 1 for SDRAM O8T_fnt Address bit 2 for SDRAM O8T_fnt Address bit 3 for SDRAM O8T_fnt Address bit 4 for SDRAM O8T_fnt Address bit 5 for SDRAM O8T_fnt Address bit 6 for SDRAM O8T_fnt Address bit 7 for SDRAM O8T_fnt Address bit 8 for SDRAM O8T_fnt Address bit 9 for SDRAM O8T_fnt Address bit 10 for SDRAM O8T_fnt Address bit 11 for SDRAM O8T_fnt Column Address Strobe for SDRAM I5_ft Scan mode reserved for device test I/O8_fnt SDRAM Data bit 0 I/O8_fnt SDRAM Data bit 1 I/O8_fnt SDRAM Data bit 2 I/O8_fnt SDRAM Data bit 3 I/O8_fnt SDRAM Data bit 4 I/O8_fnt SDRAM Data bit 5
fnt: five volts not tolerant I2_ft = I1_ft+pull up O3T_ft = O3_ft+Tristate I3_ft = I1_ft+hysteresis O6_ft = Output TTL 6mA O6DT_ft = Output TTL 6mA, Open Drain or Tristate O8T_fnt = Output CMOS 8mA I/O8_fnt = Input TTL, /Output CMOS 8mA I4_ft = I3_ft+pull up I5_ft = I3_ft+pull down;
I/O6 _ft = Input TTL/ Output TTL 6 mA O6D_ft = Output TTL 6mA, Open Drain I/O8_fnt = Input TTL, /Output CMOS 8mA; O4_fnt = Output CMOS 4mA
11/130
STLC5466
Pin N 162 163 164 165 166 167 168 169 170 171 174
Type TTL TTL TTL TTL CMOS CMOS
Symbol DM6 DM7 DM8 DM9 DM10 DM11 DM12 DM13 DM14 DM15 NTEST
ft: five volts tolerant I1_ft = Input TTL
Type I/O8_fnt SDRAM Data bit 6 I/O8_fnt SDRAM Data bit 7 I/O8_fnt SDRAM Data bit 8 I/O8_fnt SDRAM Data bit 9 I/O8_fnt SDRAM Data bit 10 I/O8_fnt SDRAM Data bit 11 I/O8_fnt SDRAM Data bit 12 I/O8_fnt SDRAM Data bit 13 I/O8_fnt SDRAM Data bit 14 I/O8_fnt SDRAM Data bit 15 I2_ft
Function
Test Control. When this pin is at 0V each output is high impedance.
fnt: five volts not tolerant I2_ft = I1_ft+pull up I3_ft = I1_ft+hysteresis O6_ft = Output TTL 6mA O6DT_ft = Output TTL 6mA, Open Drain or Tristate O8T_fnt = Output CMOS 8mA I/O8_fnt = Input TTL, /Output CMOS 8mA I4_ft = I3_ft+pull up I5_ft = I3_ft+pull down;
I/O6 _ft = Input TTL/ Output TTL 6 mA O3 _ft = Output TTL 3 mA O3T_ft = O3_ft+Tristate O6D_ft = Output TTL 6mA, Open Drain I/O8_fnt = Input TTL, /Output CMOS 8mA; O4_fnt = Output CMOS 4mA
Notes : 1. D0/15 input/output pins must be connected to one single external pull up resistor if not used.
I.1 - Pin Definition The pins of the circuit are five volts tolerant except the pins assigned to SDRAM interface. I.1.1 - Input Pin Definition I1_ft I2_ft I3_ft I4_ft I5_ft Input TTL, five volts tolerant Input 1 TTL + pull up, five volts tolerant Input 2 TTL + hysteresis, five volts tolerant Input 3 TTL + hysteresis +pull up, five volts tolerant. Input 4 TTL + hysteresis +pull down, five volts tolerant
I.1.2 - Output Pin Definition O3_ft O3T_ft O6_ft O6D_ft O6DT_ft O4_fnt O8T_fnt Output TTL 3 mA, five volts tolerant Output TTL 3 mA, Tristate, five volts tolerant Output TTL 6mA, five volts tolerant Output TTL 6mA,Open Drain, five volts tolerant Output TTL 6mA,Open Drain or Tristate. (Programmable pin), five volts tolerant Output CMOS 4mA, five volts not tolerant Output CMOS 8mA, Tristate, five volts not tolerant
Moreover, each output is high impedance when the NTEST Pin is at 0 volt. I.1.3 - Input/Output Pin Definition. I/O6_ft I/O8_fnt Input TTL/ Output TTL 6 mA five volts tolerant Input TTL/Output CMOS 8mA, five volts not tolerant
12/130
STLC5466
II - BLOCK DIAGRAM The top level functionalities of Multi-HDLC appear on the general block diagram. There are: - The switching matrix, - The 2 time slot assigners, - The 2 x 32 HDLC transmitters with associated DMA controllers, - The 2 x 32 HDLC receivers with associated DMA controllers, - The 16 Command/Indicate and Monitor Channel transmitters belonging to the two General Component Interfaces (GCI), - The 16 Command/Indicate and Monitor Channel receivers belonging to the two General Component Interfaces (GCI), - The Synchronous Dynamic Memory interface, - The microprocessor interface including Write FIFO and Fetch Memory, - The bus arbitration, - The clock selection and time synchronization function, - The interrupt controller, - The watchdog III - FUNCTIONAL DESCRIPTION III.1 - The Switching Matrix N x 64 KBits/S III.1.1 - Function Description The matrix performs a non-blocking switch of 256 time slots from 8 Input Time Division Multiplex (TDM) at 2 Mbit/s to 8 output Time Division Multiplex at 2 Mbit/s. A TDM at 2 Mbit/s consists of 32 Time Slots (TS) at 64 kbit/s. One Time Division Multiplex at 4 Mbit/s can take place of two Time Division Multiplex at 2 Mbit/s. This TDM at 4 Mbit/s is composed of 64 Time Slots (TS) at 64 kbit/s. The matrix is designed to switch a 64 kbit/s channel (Variable delay mode) or an hyperchannel of data (Sequence integrity mode). So, it will both provide minimum throughput switching delay for voice applications and time slot sequence integrity for data applications on a per channel basis. The requirements of the Sequence Integrity (n*64 kbit/s) mode are the following: All the time slots of a given input frame must be put out during a same output frame. The time slots of an hyperchannel (concatenation of TS in the same TDM) are not crossed together at output in different frames. In variable delay mode, the time slot is put out as soon as possible. (The delay is two or three time slots minimum between input and output). For test facilities, any time slot of an Output TDM (OTDM) can be internally looped back into the same Input TDM number (ITDM) at the same time slot number. A Pseudo Random Sequence Generator and a Pseudo Random Sequence Analyser are implemented in the matrix. They allow the generation of a sequence on a channel or on a hyperchannel, to analyse it and verify its integrity after several switching in the matrix or some passing of the sequence across different boards. The Frame Signal (FS) synchronises ITDM and OTDM but a programmable delay or advance can be introduced separately on each ITDM and OTDM (a half bit time, a bit time or two bit times). An additional pin (PSS) permits the generation of a programmable signal composed of 256 bits per frame at a bit rate of 2048 kbit/s. The programmation of this signal is performed thanks to PS bit of Connection Memory. An external pin (NDIS) asserts a high impedance on all the TDM outputs of the matrix when active (during the initialization of the board for example). III.1.2 - Architecture of the Matrix The matrix is essentially composed of buffer data memories and a Connection Memory. The received serial data is first converted to parallel by a serial to parallel converter and stored consecutively in a 256 position Buffer Data Memory (see Figure). To satisfy the Sequence Integrity (n*64 kbit/s) requirements, the data memory is built with an even memory, an odd memory and an output memory. Two consecutive frames are stored alternatively in the odd and even memory. During the time an input frame is stored, the one previously stored is transferred into the output memory according to the connection memory switching orders. A frame later, the output memory is read and data is converted to serial and transferred to the output TDM. III.1.3 - Connection Function Two types of connections are offered: - unidirectional connection and - bidirectional connection. An unidirectional connection makes only the switch of an input time slot through an output one whereas a bidirectional connection establishes the link in the other direction too. So a double connection can be achieved by a single command (see Figure).
13/130
STLC5466
Figure 1 : BLOCK DIAGRAM NDIS DOUT 0 DOUT 1 DOUT 2 DOUT 3 DOUT 4 DOUT 5 DOUT 6
GCI1 GCI0
0 1 2 3 4 5 6
D6
SWITCHING MATRIX 0 n x 64 kb/s 1 Scrambler/Descrambler 2 for 32 channels
Pseudo Random Sequence Analyser Pseudo Random Sequence Generator
DOUT 7
V10b
DIN 7 DIN 6
DIN 5 DIN 4 DIN 3 DIN 2 DIN 1 DIN 0
GCI0 GCI1
V10a
7
RX GCI
D7
3 4 5 6 7
TX GCI
DIN 9 CB1
V10a
V10b
DIN 8 FIRST TIME SLOT ASSIGNER EC1 CB2
V10a
SECOND TIME SLOT ASSIGNER EC2
V10b
FIRST SECOND 32 RX HDLC 32 RX HDLC with Address with Address Recognition Recognition 32 RX DMAC 32 RX DMAC Internal Bus Microprocessor interface
SECOND 32 TX HDLC with CSMA CR for Contention Bus 32 TX DMAC
FIRST 32 TX HDLC with CSMA CR for Contention Bus 32 TX DMAC SDRAM Controller
BUS ARBITRATION
V10a, bit V10 of TADR1 V10b, bit V10 of TADR2 D6, bit of GCR2 D7, bit of GCR1
14/130
STLC5466
III.1.4 - Loop Back Function Any time slot of an Output TDM can be internally looped back on the time slot which has the same TDM number and the same TS number (OTDMi, TSj) ----> (ITDMi, TSj). In the case of a bidirectional connection, only the one specified by the microprocessor is concerned by the loop back (see Figure). III.1.5 - Delay through the Matrix III.1.5.1 - Variable Delay Mode In the variable delay mode, the delay through the matrix depends on the relative positions of the input and output time slots in the frame. So, some limits are fixed: - the maximum delay is a frame + 2 time slots, - the minimum delay is programmable. Three time slots if IMTD = 1, in this case n = 2 in the formula hereafter or two time slots if IMTD = 0, in this case n = 1 in the same formula (see Paragraph "Switching Matrix Configuration Register SMCR (0C)H"). All the possibilities can be ranked in three cases: a) If OTSy > ITSx + n then the variable delay is: OTSy - ITSx Time slots b) If ITSx < OTSy < ITSx+n then the variable delay is: OTSy - ITSx + 32 Time slots c) OTSy < ITSx then the variable delay is: 32 - (ITSx - OTSy) Time slots. N.B. Rule b) and rule c) are identical. For n = 1 and n = 2, (see Figure). III.1.5.2 - Sequence Integrity Mode In the sequence integrity mode (SI = 1, bit located in the Connection Memory), the input time slots are put out 2 frames later (see Figure). In this case, the delay is defined by a single expression: Constant Delay = (32 - ITSx) + 32 + OTSy So, the delay in sequence integrity mode varies from 33 to 95 time slots. III.1.6 - Connection Memory III.1.6.1 - Description The connection memory is composed of 256 locations addressed by the number of OTDM and TS (8x32). Each location permits: - to connect each input time slot to one output time slot (If two or more output time slots are connected to the same input time slot number, there is broadcasting). - to select the variable delay mode or the sequence integrity mode for any time slot. - to loop back an output time slot. In this case the contents of an input time slot (ITSx, ITDMp) is the same as the output time slot (OTSx, OTDMp). - to output the contents of the corresponding connection memory instead of the data which has been stored in data memory. - to output the sequence of the pseudo random sequence generator on an output time slot: a pseudo random sequence can be inserted in one or several time slots (hyperchannel) of the same Output TDM; this insertion must be enabled by the microprocessor in the configuration register of the matrix. - to define the source of a sequence by the pseudo random sequence analyser: a pseudo random sequence can be extracted from one or several time slots (hyperchannel) of the same Input TDM and routed to the analyser; this extraction can be enabled by the microprocessor in the configuration register of the matrix (SMCR). - to assert a high impedance level on an output time slot (disconnection). - to deliver a programmable 256-bit sequence during 125 microseconds on the Programmable synchronization Signal pin (PSS). III.1.6.2 - Access to Connection Memory Supposing that the Switching Matrix Configuration Register (SMCR) has been already written by the microprocessor, it is possible to access to the connection memory from microprocessor with the help of two registers: - Connection Memory Data Register (CMDR) and - Connection Memory Address Register (CMAR). III.1.6.3 - Access to Data Memory To extract the contents of the data memory it is possible to read the data memory from microprocessor with the help of the two registers: - Connection Memory Data Register (CMDR) and - Connection Memory Address Register (CMAR). III.1.7 - Switching at 32 Kbit/s Four TDMs can be programmed individually to carry 64 channels at 32 Kbit/s (only if these TDMs are at 2 Mbit/s). Two bits (SW0/1) located in SMCR define the type of channels of two couples of TDMs. SW0 defines TDM0 and TDM4 (GCI0) and SW1 defines TDM1 and TDM5 (GCI1). If TDM0 or/and TDM1 carry 64 channels at 32
15/130
STLC5466
Kbit/s then TDM2 or/and TDM3 are not available externally they are used internally to perform the function. See figure: Downstream switching at 32 kb/s. See figure: Upstream switching at 32 kb/s. III.1.8 - Switching at 16 Kbit/s The TDM4 and TDM5 can be GCI multiplexes. Each GCI multiplex comprises 8 GCI channels. Each GCI channel comprises one D channel at 16 Kbit/s. See figure: GCI channel definition, GCI Synchro signal delivered by the Multi-HDLC It is possible to switch the contents of 16 D channels from the 16 GCI channels to 4 timeslots of the 256 output timeslots. In the other direction the contents of an selected timeslot is automatically switched to 4 D channels at 16 Kbit/s. See Connection Memory Data Register CMDR (0E)H. III.2 - HDLC CONTROLLER III.2.1 - Function description Two independent HDLC controllers allow to process 64 channels. Each internal HDLC controller can run up to 32 channels in a conventional HDLC mode or in a transparent (non-HDLC) mode (configurable per channel). Each channel bit rate is programmable from 4kbit/ s to 64kbit/s. All the configurations are also possible from 32 channels (from 4 to 64 kbit/s) to one channel at 2 Mbit/s. - First HDLC controller In reception for the first HDLC controller, the contents of each time slot can directly come from the input TDM DIN8 (direct HDLC Input) or from any other TDM input after switching towards the output 7 of the matrix (configurable per time slot). In transmission, the HDLC frames are sent on the output DOUT6 and on the output CB1 (with or without contention mechanism), or are switched towards the other TDM output via the input 7 of the matrix. - Second HDLC controller In reception for the second HDLC controller, the contents of each time slot can directly come from the input TDM DIN9 (direct HDLC Input) or from any other TDM input after switching towards the output 6 of the matrix (configurable per time slot). In transmission, the HDLC frames are sent on the output DOUT7 and on the output CB2 (with or without contention mechanism), or are switched towards the other TDM output via the input 6 of the matrix. III.2.1.1 - Format of the HDLC Frame The format of an HDLC frame is the same in receive and transmit direction and shown here after. III.2.1.2 - Composition of an HDLC Frame
Opening Flag Address Field (first byte) Address Field (second byte) Command Field (first byte) Command Field (second byte) Data (first byte) Data (optional) Data (last byte) FCS (first byte) FCS (second byte) Closing Flag
- Opening Flag - One or two bytes for address recognition (reception) and insertion (transmission) - Data bytes with bit stuffing - Frame Check Sequence: CRC with polynomial G(x) = x16 +x12+x5+1 - Closing Flag. III.2.1.3 - Description and Functions of the HDLC Bytes - FLAG The binary sequence 01111110 marks the beginning and the end of the HDLC Frame. Note: In reception, three possible flag configuration are allowed and correctly detected: - two normal consecutive flags: ...01111110 01111110... - two consecutive flags with a "0" common: ...011111101111110... - a global common flag:...01111110... this flag is the closing flag for the current frame and the opening flag for the next frame - ABORT The binary sequence 1111111 marks an Abort command. In reception, seven consecutive 1's, inside a message, are detected as an abort command and generates an interrupt to the host. In transmit direction, an abort is sent upon command of the micro-processor. No ending flag is expected after the abort command.
16/130
STLC5466
- BIT STUFFING AND UNSTUFFING This operation is done to avoid the confusion of a data byte with a flag. In transmission, if five consecutive 1's appear in the serial stream being transmitted, a zero is automatically inserted (bit stuffing) after the fifth "1". In reception, if five consecutive "1" followed by a zero are received, the "0" is assumed to have been inserted and is automatically deleted (bit unstuffing). - FRAME CHECK SEQUENCE The Frame Check Sequence is calculated according to the recommendation Q921 of the CCITT. - ADDRESS RECOGNITION In the frame, one or two bytes are transmitted to indicate the destination of the message. Two types of addresses are possible: - a specific destination address - a broadcast address. In reception, the controller compares the receive addresses to internal registers, which contain the address message. 4 bits in the receive command register (HRCR) inform the receiver of which registers, it has to take into account for the comparison. The receiver compares the two address bytes of the message to the specific board address and the broadcast address. Upon an address match, the address and the data following are written to the data buffers; upon an address mismatch, the frame is ignored. So, it authorizes the filtering of the messages. If no comparison is specified, each frame is received whatever its address field. In Transmission, the controller sends the frame including the destination or broadcast addresses. III.2.2 - CSMA/CR Capability An HDLC channel can come in and go out by any TDM input on the matrix. For time constraints, direct HDLC Access is achieved by the input TDM (DIN 8 for the first HDLC controller and DIN9 for the second HDLC controller) and the output TDM (DOUT6 for the first and DOUT7 for the second HDLC controller). In transmission, a time slot of a TDM can be shared between different sources in Multi-point to point configuration (different subscriber's boards for example). The arbitration system is the CSMA/ CR (Carrier Sense Multiple access with Contention Resolution). The contention is resolved by a bus connected to the CB1 pin (Contention Bus) for the first HDLC controller and CB2 pin for the second HDLC controller. These two bus are respectively a 2Mbit/s wire line common to all the potential sources. If the first HDLC controller (or the second) has obtained the access to the bus, the data to transmit is sent simultaneously on the CB1 line (or the CB2 line) and the output TDM. The result of the contention is read back on the Echo line (EC1or EC2). If a collision is detected, the transmission is stopped immediately. A contention on a bit basis is so achieved. Each message to be sent with CSMA/ CR has a priority class (PRI = 8, 10) indicated by the Transmit Descriptor and some rules are implemented to arbitrate the access to the line. The CSMA/CR Algorithm is given. When a request to send a message occurs, the transmitter determines if the shared channel is free. The MultiHDLC listens to the Echo line. If C or more consecutive "1" are detected (C depending on the message's priority), the Multi-HDLC begins to send its message. Each bit sent is sampled back and compared with the original value to send. If a bit is different, the transmission is instantaneously stopped (before the end of this bit time) and will restart as soon as the Multi-HDLC will detect that the channel is free without interrupting the microprocessor. After a successful transmission of a message, a programmable penalty PEN(1 or 2) is applied to the transmitter. It guarantees that the same transmitter will not take the bus another time before a transmitter which has to send a message of same priority. In case of a collision, the frame which has been aborted is automatically retransmitted by the DMA controller without warning the microprocessor of this collision. The frame can be located in several buffers in external memory. The collision can be detected from the second bit of the opening frame to the last but one bit of the closing frame. III.2.3 - Time Slot Assigner Memory Each HDLC channel is bidirectional and is defined by two Time Slot Assigners (TSA). TSA is a memory of 32 words (one per physical Time Slot) where all of the 32 input and output time slots of the HDLC controllers can be associated to logical HDLC channels. Super channels are created by assigning the same logical channel number to several physical time slots. The following features are programmed for each HDLC time slot: - Time slot used or not - One logical channel number - Its source: - DIN 8 or the output 7 of the matrix for the first Time Slot Assigner
17/130
STLC5466
- DIN 9 or the output 6 of the matrix for the second Time Slot Assigner. - Its bit rate and concerned bits (4kbit/s to 64kbit/ s). 4kbit/s correspond to one bit transmitted each two frames. This bit is repeated twice in transmission. This bit must be present in two consecutive frames in reception. - Its destination for the first Time Slot Assigner: - direct output on DOUT6 - direct output on DOUT6 and on the Contention Bus (CB1) - on another OTDM via input 7 of the matrix and on the Contention Bus (CB1) - Its destination for the second Time Slot Assigner: - direct output on DOUT7 - direct output on DOUT7 and on the Contention Bus (CB2) - on another OTDM via input 6 of the matrix and on the Contention Bus (CB2) III.2.4 - Data Storage Structure Data associated with each Rx and Tx HDLC channel is stored in external memory; The data transfers between the HDLC controllers and memory are ensured by 2*32 DMAC (Direct Memory Access Controller) in reception and 2*32 DMAC in transmission. The storage structure chosen in both directions is composed of one circular queue of buffers per channel. In such a queue, each data buffer is pointed to by a Descriptor located in external memory too. The main information contained in the Descriptor is the address of the Data Buffer, its length and the address of the next Descriptor; so the descriptors can be linked together. This structure allows to: - Store receive frames of variable and unknown length - Read transmit frames stored in external memory by the host - Easily perform the frame relay function. III.2.4.1 - Reception At the initialization of the application, the host has to prepare two Initialization Block registers. Each Initialization Block located in shared memory contains the first receive buffer descriptor address for each channel, and the receive circular queues. At the opening of a receive channel, the DMA controller reads the address of the first buffer descriptor corresponding to this channel in the initialization Block. Then, the data transfer can occur without intervention of the processor. A new HDLC frame always begins in a new buffer. A long frame can be split between several buffers if the buffer size is not sufficient. All the information concerning the frame and its location in the circular queue is included in the Receive Buffer Descriptor: - The Receive Buffer Address (RBA), - The size of the receive buffer (SOB), - The number of bytes written into the buffer (NBR), - The Next Receive Descriptor Address (NRDA), - The status concerning the receive frame, - The control of the queue. III.2.4.2 - Transmission In transmission, the data is managed by a similar structure as in reception By the same way, a frame can be split up between consecutive transmit buffers. The main information contained in the Transmit Descriptor are: - transmit buffer address (TBA), - number of bytes to transmit (NBT) concerning the buffer, - next transmit descriptor address (NTDA), - status of the frame after transmission, - control bit of the queue, - CSMA/CR priority (8 or 10). III.2.4.3 - Frame Relay The principle of the frame relay is to transmit a frame which has been received without treatment. A new heading is just added. This will be easily achieved, taking into account that the queue structure allows the transmission of a frame split between several buffers. III.2.5 - Transparent Modes In the transparent mode, the Multi-HDLC transmits data in a completely transparent manner without performing any bit manipulation or Flag insertion. The transparent mode is per byte function; the channel used for this mode is n*64kb/s mandatory. Two transparent modes are offered: - First mode: for the receive channels, the MultiHDLC continuously writes received bytes (from the received timeslot) into the external memory as specified in the current receive descriptor without taking into account the Fill Character Register. - Second mode: the Fill Character Register specifies the "fill character" which must be taken into account. In reception, the "fill character" is de-
18/130
STLC5466
tected in each timeslot and will not be transferred to the external memory. The detection of "Fill character" marks the end of a message and generates an interrupt if BINT=1). When the "Fill character" is not detected a new message is receiving. As for the HDLC mode the correspondence between the physical time slot and the logical channel is fully defined in the two Time Slot Assigners (Time slot used or not used, logical channel number, source, destination). III.2.6 - Command of the HDLC Channels The microprocessor is able to control each HDLC receive and transmit channel. Some of the commands are specific to the transmission or the reception but others are identical. III.2.6.1 - Reception Control - The configuration of the controller operating mode is: HDLC mode or Transparent mode. - The control of the controller: START, HALT, CONTINUE, ABORT. START: On a start command, the RxDMA controller reads the address of the first descriptor in the initialization block memory and is ready to receive a frame. HALT: For overloading reasons, the microprocessor can decide to halt the reception. The DMA controller finishes transfer of the current frame to external memory and stops. The channel can be restarted on CONTINUE command. CONTINUE: The reception restarts in the next descriptor. ABORT: On an abort command, the reception is instantaneously stopped. The channel can be restarted on a START or CONTINUE command. - Reception of FLAG (01111110) or IDLE (11111111) between Frames. - Address recognition. The microprocessor defines the addresses that the Rx controller has to take into account. - In transparent mode: "fill character" register is selected or not. III.2.6.2 - Transmission Control - The configuration of the controller operating mode is: HDLC mode or Transparent mode. - The control of the controller: START, HALT, CONTINUE, ABORT.
CGI Channel 0 TS0 B1 TS1 B2 TS2 MON TS3 S/C CGI Channel 1 to Channel 6 TS28 B1
START: On a start command, the Tx DMA controller reads the address of the first descriptor in the initialization block memory and tries to transmit the first frame if End Of Queue is not at "1". HALT: The transmitter finishes to send the current frame and stops.The channel can be restarted on a CONTINUE command. CONTINUE: if the CONTINUE command occurs after HALT command, the HDLC Transmitter restarts by transmitting the next buffer associated to the next descriptor. If the CONTINUE command occurs after an ABORT command which has occurred during a frame, the HDLC transmitter restarts by transmitting the frame which has been effectively aborted by the microprocessor. ABORT: On an abort command, the transmission of the current frame is instantaneously stopped, an ABORT sequence "1111111" is sent, followed by IDLE or FLAG bytes. The channel can be restarted on a START or CONTINUE command. - Transmission of FLAG (01111110) or IDLE (111111111) between frames can be selected. - CRC can be generated or not. If the CRC is not generated by the HDLC Controller, it must be located in the shared memory. - In transparent mode: "fill character" register can be selected or not. III.3 - C/I and Monitor III.3.1 - Function Description The Multi-HDLC is able to operate both GCI and V* links. The TDM DIN/DOUT 4 and 5 are internally connected to the CI and Monitor receivers/transmitters. Since the controllers handle up to 16CI and 16 Monitor channels simultaneously, the Multi-HDLC can manage up to 16 level 1 circuits. The Multi-HDLC can be used to support the CI and monitor channels based on the following protocols: - ISDN V* protocol - ISDN GCI protocol - Analog GCI protocol. III.3.2 - GCI and V* Protocol A TDM can carry 8 GCI channels or V* channels. The monitor and S/C bytes always stand at the same position in the TDM in both cases.
CGI Channel 7 TS29 B2 TS30 MON TS31 S/C
19/130
STLC5466
The GCI or V* channels are composed of 4 bytes and have both the same general structure.
B1 B2 MON S/C
B1, B2 : Bytes of data. Those bytes are not affected by the monitor and CI protocols. MON : Monitor channel for operation and maintenance information. S/C : Signalling and control information. Only Monitor handshakes and S/C bytes are different in the three protocols: ISDN V* S/C byte
D 2 bits C/I 4 bits T E
III.3.4 - CI and Monitor Channel Configuration Monitor channel data is located in a time slot; the CI and monitor handshake bits are in the next time slot. Each channel can be defined independently. A table with all the possible configurations is presented hereafter (Table 13). Table 13: C/I and MON Channel Configuration
C/I validated or not Monitor validated or not CI For analog subscriber (6 bits) CI For ISDN subscriber (4 bits) Monitor V* Monitor GCI
ISDN GCI S/C byte
D 2 bits C/I 4 bits A E
Note: A mix of V* and GCI monitoring can be performed for two distinct channels in the same application.
Analog GCI S/C byte
C/I 6 bits A E
CI : The Command/Indicate channel is used for activation/deactivation of lines and control functions. D : These 2 bits carry the 16 kbit/s ISDN basic access D channel. In GCI protocol, A and E are the handshake bits and are used to control the transfer of information on monitor channels.The E bit indicates the transfer of each new byte in one direction and the A bit acknowledges this byte transfer in the reverse direction. In V* protocol, there isn't any handshake mode.The transmitter has only to mark the validity of the Monitor byte by positioning the E bit (T is not used and is forced to "1"). For more information about the GCI and V*, refer to the General Interface Circuit Specification (issue1.0, march 1989) and the France Telecom Specification about ISDN Basic Access second generation (November 1990). III.3.3 - Structure of the Treatment In reception GCI/V* TDM's are connected to DIN 4 and DIN 5. The D channels are switched through the matrix towards the output 7 and output6 then towards the HDLC receivers. The Monitor and S/C bytes are multiplexed and sent to the CI and Monitor receivers. In transmission, the S/C and Monitor bytes are recombined by multiplexing the information provided by the Monitor, C/I and the HDLC Transmitter. Like in reception, the D channel is switched through the matrix (input 7 towards DOUT 4 and DOUT 5).
20/130
III.3.5 - CI and Monitor Transmission/Reception Command The reception of C/I and Monitor messages are managed by two interrupt queues. In transmission, a transmit command register is implemented for each C/I and monitor channel (16C/I transmit command registers and 16 Monitor transmit command registers). Those registers are accessible in read and write modes by the microprocessor. III.4 - Scrambler and Descrambler The TDM4 and TDM5 can be GCI multipexes. Each GCI multipex comprises 8 GCI channels. Each GCI channel comprises two B channels at 64 Kbit/s. In reception it is possible to switch and to scramble the contents of 32 B channels of GCI channels to 32 timeslots of the 256 output timeslots. In transmission these 32 timeslots are assigned to 32 B channels. In the other direction the contents of an selected B channels is automatically switched and descrambled to one B channel of 16 GCI channel. See SCR bit of Connection Memory Data Register CMDR (0E)H. III.5 - Connection between "ISDN channels" and GCI channels. Three timeslots are assigned to one "ISDN channels". Each "ISDN channels" comprises three channels: B1+B2+B* with B*= D1,D2, A, E, S1, S2, S3, S4 (See figure). - Upstream. From GCI channels to ISDN channels. * in reception: 16 GCI channels (B1+B2+MON+ D+C/I),
STLC5466
* in transmission: 16 ISDN channels (B1+B2+B*). It is possible to switch the contents of B1, B2 and D channels from 16 GCI channels in any 16 "ISDN channels", TDM side. The contents of B1 and/or B2 can be scrambled or not. If scrambled the number of the 32 timeslots (TDM side) are different mandatory. Receiving the contents of Monitor and Command / Indicate channels from 16 GCI channels. Primitives and messages are stored automatically in the external shared memory. Transmitting "six bit word" (A, E, S1, S2, S3, S4) to any 16 "ISDN channels" TDM side or not. See SBV bit of General Configuration Register GCR (02)H. - Downstream. From ISDN channels to GCI channels. * in reception: ISDN channel (B1+B2+B*) * in transmission: GCI channel (B1+B2+MON+ D+C/I) It is possible to switch the contents of B1, B2 and D channels from 16 "ISDN channels", TDM side in 16 GCI channels. The contents of B1 and/or B2 can be descrambled or not. If descrambled the 32 B1/B2 belong to GCI channels mandatory. Receiving six bit word (A, E, S1, S2, S3, S4) from any 16 "ISDN channels", TDM side. The 16 "six bit word" are stored automatically in the external shared memory. Transmitting the contents of Monitor and Command / Indicate channels to 16 GCI channels. See SBV bit of General Configuration Register GCR (02)H. - Alarm Indication Signal. This detection concerns 16 hyperchannels. One hyperchannel comprises 16 bits (B1 and B2 only). The Alarm Indications for the 16 hyperchannels are stored automatically in the external shared memory. See AISD bit of Switching Matrix Configuration Register SMCR (0C)H. III.6 - Microprocessor Interface III.6.1 - Description The Multi-HDLC circuit can be controlled by several types of microprocessors (ST9/10, Intel/Motorola 8 or 16 data bits interfaces) such as: - ST9/10 family - INTEL 80C188 8 bits - INTEL 80C186 16 bits - INTEL 386EX 16 bits - MOTOROLA 68000 16 bits - MOTOROLA 68020 32 bits Table 14: Microprocessor Interface Selection
MOD2 Pin 0 1 1 0 0 1 1 0 MOD1 Pin 1 1 0 0 0 0 1 1 MOD0 Pin 1 1 0 0 1 1 0 0 Microprocessor 80C188 80C186 68000 68020 ST9 ST10 A/D multiplexed ST10 A/D Not multiplexed 386EX
During the initialization of the Multi-HDLC circuit, the microprocessor interface is informed of the type of microprocessor that is connected by polarisation of three external pins MOD 0/2. Three chip Select (CS0/2) pins are provided. CS0 will select the internal registers and CS1 the external memory. CS2 can be used to select the external memory in INTEL 386EX application only (see pin 41 definition). III.6.2 - Buffer A Buffer is located in the microprocessor interface. It is used whatever microprocessor selected thanks to MOD0/2 pins. It allows to reduce the shared memory access cycles for the microprocessor. This Buffer consists of one Write FIFO and one Read Fetch Memory (see Figure). III.6.2.1 - Write FIFO When the microprocessor delivers the address word named Ax to write data named [Ax] in the shared memory in fact it writes data [Ax] and address word Ax in the Write FIFO (8 words). If Ax is in Fetch Memory, [Ax] is removed in Fetch Memory. There is no wait time for the microprocessor if the Write FIFO is not full entirely.
21/130
STLC5466
Shared memory
SDRAM Bus
To shared memory
SDRAM Controller
From shared memory
MHDLC Internal Bus
Ax, [Ax] Ay, [Ay] Az, [Az] At, [At] Up to eight words Input register used to store data in Write FIFO from microprocessor Write FIFO
Read Fetch Memory
64 words Fetch Memory An, [An]
MHDLC microprocessor interface
To microprocessor
Microprocessor Bus
Microprocessor
Figure 2 : Exchange between Microprocessor and Shared memory across MHDLC
22/130
STLC5466
III.6.2.2 - Read Fetch Memory When the microprocessor delivers the address word named An to read data named [An] out of the shared memory in fact it reads data [An] from the Read Fetch Memory (64 words). The number of wait cycle for the microprocessor is strongly reduced. If An, address word delivered by the microprocessor, and data [An] are already in the Read Fetch Memory and validated then there is no wait time for the microprocessor. The source of [An] is truly the shared memory whatever An. Data [An] if validated in Fetch Memory and Data [An] in shared memory are always the same. III.6.2.3 - Definition of the Interface for the different microprocessors The signals connected to the microprocessor interface are presented on the following figures for the different microprocessor (see Figures). III.7 - Memory Interface III.7.1 - Function Description The memory interface allows the connection of Synchronous Dynamic RAM. The memory interface will address up to 16 Megabytes. The memory location is always organized in 16 bits. The memory is shared between the Multi-HDLC and the microprocessor. The access to the memory is arbitrated by an internal function of the circuit: the bus arbitration. III.7.2 - Choice of memory versus microprocessor and capacity required The memory interface depends on the memory chips which are connected. The memory chips will be chosen versus their organization. Example1: if the application requires 8 or 16 bit Processor and 1 Megaword Shared memory size, one capability is offered: - 1 SDRAM Circuit (1Mx16). Example2: if the application requires 16 bit Processor and 4 Megaword Shared memory size, three capabilities are offered: - 4 SDRAM Circuits (1Mx16) or - 4 SDRAM Circuits (4Mx4) or - 1 SDRAM Circuit (4Mx16). .Example3: if the application requires 8 Megaword Shared memory size three capabilities are offered: - 8 SDRAM Circuits (4Mx4) or - 2 SDRAM Circuits (4Mx16) or - 2 SDRAM Circuit (8Mx8). III.7.3 - Memory Cycle Some parameters are frozen: - Burst Read and Single Write. - The Burst Length is 4. - The burst data is addressed in sequential mode. The programmable parameters are: - Latency Mode - selected circuit organisation - the exchanges between Multi-HDLC and SDRAM are at the Master Clock frequency (33MHz, 50MHz, 66MHz) III.7.4 - Memories composed of different circuits III.7.4.1 - Memory obtained with 1M x16 SDRAM circuit
Signals NCE3 NCE2 NCE1 NCE0 A22 1 1 0 0 A21 1 0 1 0 UDQM LDQM 1 0 Signals A0 or equivalent
The Address bits delivered by the Multi-HDLC for 1M x 16 SDRAM circuits are: - ADM11 for Bank select corresponding with A20 delivered by the microprocessor - ADM0/10 for Row address inputs corresponding with A9/19 delivered by the microprocessor - ADM0/7 for Column address inputs corresponding with A1/8 delivered by the microprocessor III.7.4.2 - Memory obtained with 2M x 8 SDRAM circuit
Signals UDQM LDQM A0 or equivalent 1 0 NLDS 0 1 NUDS 1 0
The Address bits delivered by the Multi-HDLC for 2M x 8 SDRAM circuits are: - ADM11 for Bank select corresponding with A21 delivered by the microprocessor - ADM0/10 for Row address inputs corresponding with A10/20 delivered by the microprocessor - ADM0/8 for Column address inputs corresponding with A1/9 delivered by the microprocessor
23/130
STLC5466
III.7.4.3 - Memory obtained with 8M x 8 SDRAM circuit
Signals UDQM LDQM A0 or equivalent 1 0 NLDS 0 1 NUDS 1 0
The Address bits delivered by the Multi-HDLC for 8M x 8 SDRAM microprocessor circuits are: - ADM12/13 for Bank select corresponding with A22/23 delivered by the microprocessor - ADM0/11 for Row address inputs corresponding with A10/21 delivered by the microprocessor - ADM0/8 for Column address inputs corresponding with A1/9 delivered by the microprocessor III.7.4.4 - Memory obtained with 4M x 16 SDRAM circuit
Signals NCE1 NCE0 A23 1 0 Signals UDQM LDQM A0 or equivalent 1 0 NLDS NUDS 0 1 1 0
The Address bits delivered by the Multi-HDLC for 4M x 16 SDRAM circuits are: - ADM12/13 for Bank select corresponding with A21/22 delivered by the microprocessor - ADM0/11 for Row address inputs corresponding with A9/20 delivered by the microprocessor - ADM0/7 for Column address inputs corresponding with A1/8 delivered by the microprocessor III.8 - Bus Arbitration The Bus arbitration function arbitrates the access to the bus between different entities of the circuit. Those entities which can call for the bus are the following: - The receive DMA controller, - The microprocessor, - The transmit DMA controller, - The Interrupt controller, - The memory interface for refreshing the SDRAM. This list gives the memory access priorities per default. If the treatment of more than 64 HDLC channels is required by the application, it is possible to chain several Multi-HDLC components. That is done with two external pins (TRI, TRO) and a token ring system. The TRI, TRO signals are managed by the bus arbitration function too. When a chip has finished its tasks, it sends a pulse of 30 ns to the next chip.
III.9 - Clocks III.9.1 - Clock Distribution Selection and Supervision Two clock distributions are available: Clock at 4.096 MHz or 8.192 MHz and a synchronization signal at 8 KHz. The component has to select one of these two distributions and to check its integrity. Two other clock distributions are allowed: Clock at 3072 MHz or 6144 MHz and a synchronization signal at 8 KHz. See General Configuration Register GCR (02)H. DCLK, FSC GCI and FSC V* are output on three external pins of the Multi-HDLC. DCLK is the clock selected between Clock A and Clock B. FSC, GCI and FSC V* are functions of the selected distribution and respect the GCI and V* frame synchronization specifications. The supervision of the clock distribution consists of verifying its availability. The detection of the clock absence is done in a less than 250 microseconds. In case the clock is absent, an interrupt is generated with a 4 kHz recurrence. Then the clock distribution is switched automatically up to detection of couple A or couple B. When a couple is detected the change of clock occurs on a falling edge of the new selected distribution. Moreover the clock distribution can be controlled by the microprocessor thanks to SELB, bit of General Configuration Register. Depending on the applications, three different signals of synchronization (GCI, V* or Sy) can be provided to the component. The clock A/B frequency can be a 4096 or 8192 kHz clock. The component is informed of the synchronization and clocks that are connected by software. III.9.2 - VCXO Frequency Synchronization An external VCXO can be used to provide a clock to the transmission components. This clock is controlled by the main clock distribution (Clock A or Clock B at 4096kHz). As the clock of the transmission component is 15360 or 16384kHz, a configurable function is necessary. The VCXO frequency is divided by P (30 or 32) to provide a common sub-multiple (512kHz) of the reference frequency CLOCKA or CLOCKB (4096kHz). The comparison of these two signals gives an error signal which commands the VCXO. Two external pins are needed to perform this function: VCXO-IN and VCXO-OUT.
24/130
STLC5466
III.10 - Interrupt Controller III.10.1 - Description Three external pins are used to manage the interrupts generated by the Multi-HDLC. The interrupts have three main sources: - The operating interrupts generated by the HDLC receivers/transmitters, the CI receivers and the monitor transmitters/receivers. INT0 Pin is reserved for this use. - The interrupt generated by an abnormal working of the clock distribution. INT1 Pin is reserved for this use. - The non-activity of the microprocessor (Watchdog). WDO Pin is reserved for this use. III.10.2 - Operating Interrupts (INT0 Pin) There are five main sources of operating interrupts in the Multi-HDLC circuit: - The HDLC receiver, - The HDLC transmitter, - The CI receiver, - The Monitor receiver, - The Monitor transmitter. When an interrupt is generated by one of these functions, the interrupt controller: - Collects all the information about the reasons of this interrupt - Stores them in external memory. - Informs the microprocessor by positioning the INT0 pin in the high level. Three interrupt queues are built in external memory to store the information about the interrupts: - A single queue for the HDLC receivers and transmitter - One for the CI receivers - One for the monitor receiver The microprocessor takes the interrupts into account by reading the Interrupt Register (IR) of the interrupt controller. This register informs the microprocessor of the interrupt source. The microprocessor will have information about the interrupt source by reading the corresponding interrupt queue (see Paragraph "Interrupt Register IR(38)H" on Page 74). On an overflow of the circular interrupt queues and an overrun or underrun of the different FIFO, the INT0Pin is activated and the origin of the interrupt is stored in the Interrupt Register. A 16 bits register is associated with the Tx Monitor interrupt. It informs the microprocessor of which transmitter has generated the interrupt (see Paragraph "Transmit Monitor Interrupt Register TMIR(30)H" on Page 71). III.10.3 - Time Base Interrupts (INT1 Pin) The Time base interrupt is generated when an absence or an abnormal working of clock distribution is detected. The INT1 Pin is activated. III.10.4 - Emergency Interrupts (WDO Pin) The WDO signal is activated by an overflow of the watchdog register. III.10.5 - Interrupt Queues There are three different interrupt queues: - Tx and Rx HDLC interrupt queue - Rx C/I interrupt queue - Rx Monitor interrupt queue. Their length can be defined by software. For debugging function, each interrupt word of the CI interrupt queue and monitor interrupt queue can be followed by a time stamped word. It is composed of a counter which runs in the range of 250s. The counter is the same as the watchdog counter. Consequently, the watchdog function isn't available at the same time. III.11 - Watchdog This function is used to control the activity of the application. It is composed of a counter which counts down from an initial value loaded in the Timer register by the microprocessor. If the microprocessor doesn't reset this counter before it is totally decremented, the external Pin WDO is activated; this signal can be used to reset the microprocessor and all the application. The initial time value of the counter is programmable from 0 to 15s in increments of 0.25ms. At the reset of the component, the counter is automatically initialized by the value corresponding to 512ms which are indicated in the Timer register. The microprocessor must put WDR (IDCR Register) to"1" to reset this counter and to confirm that the application started correctly. In the reverse case, the WDO signal could be used to reset the board a second time. III.12 - Reset There are two possibilities to reset the circuit: - by software, - by hardware. Each programmable register receives its default value. After that, the default value of each data register is stored in the associated memory except for Time slot Assigner memory.
25/130
STLC5466
III.13 - BOUNDARY SCAN The Multi-HDLC is equipped with an IEEE Standard Test Access Port (IEEE Std 1149.1). The boundary scan technique involves the inclusion of a shift register stage adjacent to each component pin so that signals at component boundaries can be controlled and observed using scan testing principle. Its intention is to enable the test of on board interconnections and ASIC production tests. The external interface of the Boundary Scan is composed of the signals TDI, TDO, TCK, TMS and TRST as defined in the IEEE Standard.
26/130
STLC5466
IV - DC SPECIFICATIONS Absolute Maximum Ratings
Symbol VDD Parameter 3.3V Power Supply Voltage Input or Output Voltage Input or Output Voltage Tstg Storage Temperature Value -0.5V to 4V -0.5 to VDD + 0.5V -0.5 to +5.5V(see Note 1) -55 to 125 /C Unit V V V /C
Recommended DC Operating Conditions
Symbol VDD Toper Operating Temperature Parameter 3.3V Power Supply Voltage (see Note2) Min. 3.0 - 40 Typ. 3.3 Max. 3.6 85 Unit V /C
Note 1: For 5V tolerant inputs and 5V tolerant output buffers in tristate mode Note 2: All the following specifications are valid only within these recommended operating conditions .
TTL Input DC Electrical Characteristics
Symbol VIL VIH VOL VOH IIL IIH Ioz Vhyst VT+ VTParameter Low Level Input Voltage High Level Input Voltage Low Level Output Voltage High Level Output Voltage Low Level Input Current Without pull-up device High Level Input Without pull-up device Tristate output leakage current without pullup/down device Schmitt Trigger hysteresis Positive Trigger Voltage Negative Trigger Voltage IOL = X mA (see Note 3) IOH = -X mA (see Note 3) VI = 0V VI = VDD VI = VDD 0.4 0.9 0.4 2.4 1 -1 -1 0.7 1.35 0.7 2.0 0.4 Test Conditions Min. Typ. Max. 0.8 Unit V V V V A A A V V V
Note 3: X is the source /sink current under worst case conditions in accordance with the drive capability: O3 = 3mA, O4 = 4 mA
CMOS Output DC Electrical Characteristics valid only within these recommended operating conditions
Symbol VIL VIH VOL VOH Parameter Low level input voltage High level input voltage Low Level Output Voltage High Level Output Voltage Iol = XmA (see Note 4) Ioh = XmA (see Note 4) 0.85VDD 0.8VDD 0.4 Test Conditions Min. Typ. Max. 0.2VDD Unit V V V V
Note 4: X is the source/sink current under worst case conditions and is reflected in the name of the I/O cell according to the drive capability. X = 4 or 8mA
27/130
STLC5466
pull-up and pull-down characteristics
Symbol Ipu Ipd Ipd Rpu Rpd Rpd
Note5 Note6
Parameter pull-up current pull-down current pull-down current Equivalent pull-up resistance Equivalent pull-down resistance Equivalent pull-down resistance
Test Conditions Vi = 0V (Note5) Vi = Vdd (Note5) Vi = 5V (Note5) Vi = 0V Vi = Vdd Vi = 5V (Note6)
Min. -25 +25 +25
Typ. -66 +66 +66 50 50 76
Max. -125 +125 +125
Unit A uA uA KOhm KOhm KOhm
Min condition: Vdd = 3.0V, 85 degrees C. Max condition: Vdd = 3.6V, -40 degrees C. For 5V tolerant buffers
General interface Electrical Characteristics
Symbol P Cin Cout C i/o VESD
Note7
Parameter Power Dissipation Input capacitance Output capacitance Bidir I/O capacitance Electrostatic Protection
Test Conditions VDD=3.3 Volts; MCLK=66MHz Freq = 1MHz@0V (Note6) (Note7) (Note7) C = 100pF, R = 1.5k
Min.
Typ. 350 2 4
Max. 450 4
Unit mW pF pF pF V
4 2000
8
Excluding package (TQFP176, add 1.9pF)
28/130
STLC5466
V - List of registers Internal registers * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * Identification and Dynamic Command Register General Configuration Register 1 Input Multiplex Configuration Register 0 Input Multiplex Configuration Register 1 Output Multiplex Configuration Register 0 Output Multiplex Configuration Register 1 Switching Matrix Configuration Register Connection Memory Data Register Connection Memory Address Register Sequence Fault Counter Register Time Slot Assigner Address Register 1 Time Slot Assigner Data Register 1 HDLC Transmit Command Register 1 HDLC Receive Command Register 1 Address Field Recognition Address Register 1 Address Field Recognition Data Register 1 Fill Character Register 1 GCI Channels Definition Register 0 GCI Channels Definition Register 1 GCI Channels Definition Register 2 GCI Channels Definition Register 3 Transmit Command / Indicate Register Transmit Monitor Address Register Transmit Monitor Data Register Transmit Monitor Interrupt Register Memory Interface Configuration Register Initiate Block Address Register 1 Interrupt Queue Size Register Interrupt Register Interrupt Mask Register Timer Register 1 Test Register General Configuration Register 2 Split Fetch Memory Register Time Slot Assigner Address Register 2 Time Slot Assigner Data Register 2 HDLC Transmit Command Register 2 HDLC Receive Command Register 2 Address Field Recognition Address Register 2 Address Field Recognition Data Register 2 Fill Character Register 2 SDRAM Mode Register Initiate Block Address Register 2 Timer Register 2 IDCR GCR1 IMCR0 IMCR1 OMCR0 OMCR1 SMCR CMDR CMAR SFCR TAAR1 TADR1 HTCR1 HRCR1 AFRAR1 AFRDR1 FCR1 GCIR0 GCIR1 GCIR2 GCIR3 TCIR TMAR TMDR TMIR MICR IBAR1 IQSR IR IMR TIMR1 TR GCR2 SFMR TAAR2 TADR2 HTCR2 HRCR2 AFRAR2 AFRDR2 FCR2 SDRAMR IBAR2 TIMR2 (00)H (02)H (04)H (06)H (08)H (0A)H (0C)H (0E)H (10)H (12)H (14)H (16)H (18)H (1A)H (1C)H (1E)H (20)H (22)H (24)H (26)H (28)H (2A)H (2C)H (2E)H (30)H (32)H (34)H (36)H (38)H (3A)H (3C)H (3E)H (42)H (4E)H (54)H (56)H (58)H (5A)H (5C)H (5E)H (60)H (72)H (74)H (7C)H
29/130
STLC5466
External registers * * * * * * Initialization Block in External Memory (IBA1 and IBA2) Receive Descriptor Transmit Descriptor Receive & Transmit HDLC Frame Interrupt Receive Command / Indicate Interrupt Receive Monitor Interrupt
30/130
STLC5466
VI - INTERNAL REGISTERS `Not used' bits (Nu) are accessible by the microprocessor but the use of these bits by software is not recommended. `Reserved' bits are not implemented in the circuit. However, it is not recommended to use these bits. VI.1 - Identification and Dynamic Command Register
bit15 C15 C14 C13 C12 C11 C10 C9 bit8 C8 bit7 C7 C6 C5 C4 C3 C2 C1
IDCR (00) H
bit0 C0
When this register is read by the microprocessor, the circuit code C0/15 is returned. Reset has no effect on this register. C0/3 indicates the version. C4/7 indicates the revision. C8/11 indicates the foundry. C12/15 indicates the type. Example: this code is (0010)H for the first sample. When this register is written by the microprocessor then:
bit15 Nu Nu Nu Nu Nu Nu Nu bit8 Nu bit7 Nu Nu Nu Nu Nu RSS WDR bit0 TL
TL
: TOKEN LAUNCH When TL is set to 1 by the microprocessor, the token pulse is launched from the TRO pin (Token Ring Output pin). This pulse is provided to the TRI pin (Token Ring Input pin) of the next circuit in the applications where several Multi-HDLCs are connected to the same shared memory.
WDR : WATCHDOG RESET. When the bit 1 (WDR) of this register is set to 1 by the microprocessor, the watchdog counter is reset. RSS : RESET SOFTWARE When the bit 2 (RSS) of this register is set to 1 by the microprocessor, the circuit is reset (Same action as reset pin). After writing this register, the values of these three bits return to the default value. VI.2 - General Configuration Register 1
bit15 SBV MBL AFAB SCL BSEL SELB CSD bit8 HCL bit7 SYN1 SYN0 D7 EVM TSV TRD PMA
GCR1 (02)H
bit0 WDD
After reset (0000)H
WDD
: Watch Dog Disable WDD = 1, the Watch Dog is masked: WDO pin stays at "0". WDD = 0, the Watch Dog generates an "1" on WDO pin if the microprocessor has not reset the Watch Dog during the duration programmed in Timer Register. : Priority Memory Access PMA = 1, if the token ring has been launched it is captured and kept in order to authorize memory accesses. PMA = 0, memory is accessible only if the token is present; after one memory access the token is re-launched from TRO pin of the current circuit to TRI pin of the next circuit. : Token Ring Disable TRD = 1, if the token has been launched, the token ring is stopped and destroyed; memory accesses are not possible. The token will not appear on TRO pin. TRD = 0, the token ring is authorized; when the token will be launched, it will appear on TRO pin.
PMA
TRD
31/130
STLC5466
TSV : Time Stamping Validated TSV = 1, the time stamping counter becomes a free binary counter and counts down from 65535 to 0 in step of 250 microseconds (Total = 16384ms). So if an event occurs when the counter indicates A and if the next event occurs when the counter indicates B then: t = (A-B) x 250 microseconds is the time which has passed between the two events which have been stored in memory by the Interrupt Controller (for Rx C/I and Rx MON CHANNEL only). TSV = 0, the counter becomes a decimal counter.The Timer Register and this decimal counter constitute a Watch Dog or a Timer. : EXTERNAL VCXO MODE EVM=1,VCXO Synchronization Counter is divided by 32. EVM=0,VCXO Synchronization Counter is divided by 30. : First HDLC controller connected to MATRIX D7 = 1, the first transmit HDLC controller is connected to matrix input 7, the DIN7 signal is ignored. D7 = 0, the DIN7 signal is taken into account by the matrix, the first transmit HDLC controller is ignored by the matrix.
EVM
D7
SYN0/1 : SYNCHRONIZATION SYN0/1: these two bits define the signal applied on FRAMEA/B inputs.
SYN1 0 0 1 1 SYN0 0 1 0 1 SY Interface GCI Interface (the signal defines the first bit of the frame) Vstar Interface (the signal defines third bit of the frame) Not used Signal applied on FRAMEA/B inputs
HCL
: HIGH BIT CLOCK This bit defines the signal applied on CLOCKA/B inputs. HCL = 1, bit clock signal is at 8192kHz (or 6144kHz) HCL= 0, bit clock signal is at 4096kHz (or 3072kHz) : Clock Supervision Deactivation CSD = 1, the lack of selected clock is not seen by the microprocessor; INT1 is masked. CSD = 0, when the selected clock disappears the INT1 pin goes to 5V, 250ms after this disappearance. : SELECT B SELB = 1, FRAME B and CLOCK B must be selected. SELB = 0, FRAME A and CLOCK A must be selected. : B SELECTED (this bit is read only) BSEL = 1, FRAME B and CLOCK B are selected. BSEL = 0, FRAME A and CLOCK A are selected. : Single Clock This bit defines the signal delivered by DCLK output pin. CLOCKA/B inputs at 4096kHz or 8192kHz SCL = 1, Data Clock is at 2048kHz. SCL = 0, Data Clock is at 4096kHz. CLOCKA/B inputs at 3072kHz or 6144kHz SCL = 1, Data Clock is at 1536kHz. SCL = 0, Data Clock is at 3072kHz.
CSD
SELB
BSEL
SCL
32/130
STLC5466
AFAB : Advanced Frame A/B Signal AFAB = 1, the advance of FRAMEA Signal and FRAMEB Signal is 0.5 bit time versus the signal FRAMEA (or B). AFAB = 0, FRAMEA Signal and FRAMEB Signal are in accordance with the clock timing. MBL : Memory Bus Low impedance MBL = 1, the shared memory bus is at low impedance between two memory cycles and also at low impedance during a memory cycle. The memory bus includes Control bus, Address bus except Data bus. One Multi-HDLC can be connected to the shared memory. 16 pull-up resistors must be connected on the data bus. MBL = 0, the shared memory bus is at high impedance between two memory cycles and at low impedance during a write memory cycle. Several Multi-HDLCs can be connected to the shared memory. One pull-up resistor is recommended on each wire (Control bus, Address bus, Data bus).
.
During the whole of cycle duration MBL 1 D 0 A, C D L L L Z L Z Bus A, C Write cycle L Read cycle L
On the outside of cycle
L Z Z Z
SBV
: Six Bit Validation (A, E, S1/S4 bits). Global validation for 16 channels (Upstream and downstream). SBV=1, in reception, the six bit word (A, E, S1/S4) located in the same timeslot as D channel can be received from any input timeslot; when this word is received identical twice consecutively, it is stored in the external shared memory and an interrupt is generated if not masked (like the reception of primitive from C/I channel). Sixteen independent detections are performed if the contents of any input timeslot is switched in the timeslot 4n+3 of two GCI multiplexes (corresponding to DOUT4 and DOUT5) with (0 n 7). Only the contents of D channel will be transmitted from input timeslot to GCI multiplexes. In transmission a six bit word (A, E, S1/S4) can be transmitted continuously to any output timeslot via the TCIR. This word (A, E, S1/S4) is set instead of primitive (C1, C2, C3, C4) and A, E bits received from the timeslot 4n+3 of two GCI multiplexes and the new contents of this timeslot 4n+3 must be switched on the selected output timeslot. SBV=0, the 16 six bit detections are not validated. IMCR0 (04)H
bit7 bit0
VI.3 - Input Multiplex Configuration Register 0
bit15 bit8
LP3 DEL3 ST(3)1 ST(3)0 LP2 DEL2 ST(2)1 ST(2)0 LP1 DEL1 ST(1)1 ST(1)0 LP0 DEL0 ST(0)1 ST(0)0 After reset (0000)H
See definition in next Paragraph.
33/130
STLC5466
VI.4 - Input Multiplex Configuration Register 1
bit15 bit8 bit7
IMCR1 (06)H
bit0
LP7 DEL7 ST(7)1 ST(7)0 LP6 DEL6 ST(6)1 ST(6)0 LP5 DEL5 ST(5)1 ST(5)0 LP4 DEL4 ST(4)1 ST(4)0 After reset (0000)H
ST(i)0 : STEP0 for each Input Multiplex(i) with (0 i 7), delayed or not. ST(i)1 : STEP1 for each Input Multiplex(i) with (0 i 7), delayed or not. DEL(i) : DELAYED Multiplex i(0 i 7).
.
DEL (i) X 1 1 1 0 0 0
ST (i) 1 0 0 1 1 0 1 1
ST (i) 0 0 1 0 1 1 0 1
STEP for each Input Multiplex 0/7 delayed or not Each received bit is sampled at 3/4 bit-time without delay (TDM at 2 Mb/s).First bit of the frame is defined by Frame synchronization Signal. Each received bit is sampled with 1/2 bit-time delay Each received bit is sampled with 1 bit-time delay Each received bit is sampled with 2 bit-time delay Each received bit is sampled with 1/2 bit-time advance Each received bit is sampled with 1 bit-time advance Each received bit is sampled with 2 bit-time advance
When IMTD = 0 (bit of SMCR), DEL = 1 is not taken into account by the circuit. If TDM is at 2048 kb/s,1/2 bit-time is 244 ns, If TDM is at 4096 kb/s,1/2 bit-time is 122 ns. LP (i) : LOOPBACK 0/7 LPi = 1, Output Multiplex(i) is put instead of Input Multiplex(i) with (0 i 7). LOOPBACK is transparent or not in accordance with OMVi (bit of Output Multiplex Configuration Register). LPi = 0, Normal case, Input Multiplex(i) with (0 i 7) is taken into account.
N.B. If DIN4 and DIN5 are GCI Multiplexes: then ST(4)1 = ST(4)0 = 0 and ST(5)1 = ST(5)0 = 0 normally.
VI.5 - Output Multiplex Configuration Register 0
bit15 bit8 bit7
OMCR0 (08)H
bit0
OMV3 DEL3 ST(3)1 ST(3)0 OMV2 DEL2 ST(2)1 ST(2)0 OMV1 DEL1 ST(1)1 ST(1)0 OMV0 DEL0 ST(0)1 ST(0)0 After reset (0000)H
See definition in next Paragraph. VI.6 - Output Multiplex Configuration Register 1
bit15 bit8 bit7
OMCR1 (0A)H
bit0
OMV7 DEL7 ST(7)1 ST(7)0 OMV6 DEL6 ST(6)1 ST(6)0 OMV5 DEL5 ST(5)1 ST(5)0 OMV4 DEL4 ST(4)1 ST(4)0 After reset (0000)H
ST(i)0 : STEP0 for each Output Multiplex(i) with (0 i 7), delayed or not. ST(i)1 : STEP1 for each Output Multiplex(i) with (0 i 7), delayed or not.
34/130
STLC5466
DEL(i); : DELAYED Multiplex(i) with (0 i 7).
DEL (i) X 1 1 1 0 0 0 ST (i) 1 0 0 1 1 0 1 1 ST (i) 0 0 1 0 1 1 0 1 STEP for each Output Multiplex 0/7 delayed or not Each bit is transmitted on the rising edge of the double clock without delay. Bit0 is defined by Frame synchronization Signal. Each bit is transmitted with 1/2 bit-time delay. Each bit is transmitted with 1 bit-time delay. Each bit is transmitted with 2 bit-time delay Each bit is transmitted with 1/2 bit-time advance. Each bit is transmitted with 1 bit-time advance. Each bit is transmitted with 2 bit-time advance
When IMTD = 0 (bit of SMCR), DEL = 0 is not taken into account by the circuit. If TDM is at 2048 kb/s,1/2 bit-time is 244 ns If TDM is at 4096 kb/s,1/2 bit-time is 122 ns OMV (i) : Output Multiplex Validated 0/7 OMVi =1, condition to have DOUT(i) pin active (0 i 7). OMVi =0, DOUT(i) pin is High impedance continuously (0 i 7).
N.B. If DOUT4 and DOUT5 are GCI Multiplexes: then ST(4)1 = ST(4)0 = 0 and ST(5)1 = ST(5)0 = 0 normally.
VI.7 - Switching Matrix Configuration Register
bit15 SW1 SW0 M1 M0 bit8 bit7 ME SGC SAV SGV TS1 DR64 DR44 DR24 DR04 AISD After reset (0000)H
SMCR (0C)H
bit0 TS0 IMTD
IMTD
: Increased Minimum Throughput Delay When SI = 0 (bit of CMDR, variable delay mode): IMTD = 1, the minimum delay through the matrix memory is three time slots whatever the selected TDM output. IMTD = 0, the minimum delay through the matrix memory is two time slots whatever the selected TDM output. In this case the input TDM's cannot be delayed versus the Frame Synchronization (use of IMCR is limited) and the output TDM's cannot be advanced versus the Frame Synchronization (use of OMCR is limited). : Tristate 0 TS0 = 1, the DOUT0/3 and DOUT6/7 pins are tristate: "0" is at low impedance, "1" is at low impedance and the third state is high impedance. TS0 = 0, the DOUT0/3 and DOUT6/7 pins are open drain: "0" is at low impedance, "1" is at high impedance. : Tristate 1 TS1 = 1, the DOUT4/5 pins are tristate: "0" is at low impedance, "1" is at low impedance and the third state is high impedance. TS1 = 0, the DOUT4/5 pins are open drain: "0" is at low impedance, "1" is at high impedance. : Pseudo Random Sequence Generator Validated SGV = 1,PRS Generator is validated.The Pseudo Random Sequence is transmitted during the related time slot(s). SGV = 0, PRS Generator is reset."0" are transmitted during the related time slot.
TS0
TS1
SGV
35/130
STLC5466
SAV : Pseudo Random Sequence analyser Validated SAV = 1, PRS analyser is validated. SAV = 0, PRS analyser is reset. : Pseudo Random Sequence Generator Corrupted When SGC bit goes from 0 to 1, one bit of sequence transmitted is corrupted. When the corrupted bit has been transmitted, SGC bit goes from 1 to 0 automatically. : MESSAGE ENABLE ME = 1 The contents of Connection Memory is output on DOUT0/7 continuously. ME = 0 The contents of Connection Memory acts as an address for the Data Memory. : Alarm Indication Signal Detection. AISD=1, the Alarm Indication Signal detection is validated. Sixteen independent detections are performed for sixteen hyperchannels. The contents of any input hyperchannel (B1, B2) switched (in transparent mode or not) on GCI channels is analysed independently. For each GCI channel, the 16 bits of B1and B2 channels are checked together; when all "one" has been detected during 30 milliseconds, a status is stored in the Command/ Indicate interrupt queue and an interrupt is generated if not masked (like the reception of primitive from GCI multiplexes). AISD=0, the Alarm Indication Signal detection for 16 hyperchannels is not validated.
SGC
ME
AISD
DR04
: Data Rate of TDM0 is at 4Mb/s (Case: M1=M0=0). DR04 = 1, the signal received from DIN0 pin and the signal delivered by Dout0 pin are at 4Mb/ s. DIN1 pin and DOUT1 pin are ignored. The Time Division Multiplex 0 is constituted by 64 contiguous timeslots numbered from 0 to 63. DR04 = 0, the signals received from DIN0/1 pins and the signals delivered by Dout0/1 pins are at 2Mb/s. : Data Rate of TDM2 is at 4Mb/s (Case: M1=M0=0). DR24 = 1, the signal received from DIN2 pin and the signal delivered by Dout2 pin are at 4Mb/ s. DIN3 pin and DOUT3 pin are ignored. The Time Division Multiplex 2 is constituted by contiguous 64 timeslots numbered from 0 to 63. DR24 = 0, the signals received from DIN2/3 pins and the signals delivered by Dout2/3 pins are at 2Mb/s. : Data Rate of TDM4 is at 4Mb/s (Case: M1=M0=0). DR44 = 1, the signal received from DIN4 pin and the signal delivered by Dout4 pin are at 4Mb/ s. DIN5 pin and DOUT5 pin are ignored. TDM4/5 cannot be GCI multiplexes. The Time Division Multiplex 4 is constituted by 64 contiguous timeslots numbered from 0 to 63. DR44 = 0, the signals received from DIN4/5 pins and the signals delivered by Dout4/5 pins are at 2Mb/s.
DR24
DR44
DR64
: Data Rate of TDM6 is at 4Mb/s (Case: M1=M0=0). . DR64 = 1, the signal received from DIN6 pin and the signal delivered by Dout6 pin are at 4Mb/ s. DIN7 pin and DOUT7 pin are ignored. The Switching Matrix cannot be used to switch the channels to/from the HDLC controllers but the RX HDLC controller can be connected to DIN8 and the TX HDLC controller can be connected to CB pin. The Time Division Multiplex 6 is constituted by 64 contiguous timeslots numbered from0 to 63. DR64 = 0, the signals received from DIN6/7 pins and the signals delivered by Dout6/7 pins are at 2M b/s.
36/130
STLC5466
M1/0 : Data Rate of TDM0/8; These two bits indicate the data rate of height Time Division Multiplexes TDM0/7 relative to DIN0/7 and DOUT0/7. The table below shows the different data rates with the clock frequency defined by HCL bit (General Configuration Register). N.B. The data rate of the Time Division Multiplex relative to DIN8, CB and Echo pins are at 2048 Kbit/s or1536 Kbit/s depending on M1/0 only.
M1 M0 Data Rate of TDM0/7 in Kbit/s CLOCKA/B signal frequency HCL=0 0 0 1 1 0 1 0 1 2048 (or 4096 in accordance with DR0x4) 1536 (or 3072 in accordance with DR0x4) Reserved Reserved 4096 KHz 3072 KHz HCL=1 8192 KHz 6144KHz
SW0
: Switching at 32 Kbit/s for the TDM0 (DIN0/DOUT0) SW0=1, DIN0 can receive 64 channels at 32 Kbit/s. DIN2/DOUT2 are not available. DIN2 is used to receive internally TDM0 (DIN0) after 4 bit shifting DOUT2 is used to multiplex internally TDM2 and TDM4. SW0=0, DIN0 receives 32 (or 24) channels at 64 Kbit/s or 64 channels at 64 Kbit/s depending on DR04 bit and ClockA/B. : Switching at 32 Kbit/s for the TDM1 (DIN1/DOUT1) SW1=1, DIN1 can receive 64 channels at 32 Kbit/s. DIN3/DOUT3 are not available. DIN3 is used to receive internally TDM1(DIN1) after 4 bit shifting DOUT3 is used to multiplex internally TDM3 and TDM5. SW1=0, DIN1 receives 32 (or 24) channels at 64 Kbit/s or 64 channels at 64 Kbit/s depending on DR04 bit and ClockA/B. CMDR (0E) H
SOURCE REGISTER (SRCR) bit8 PS PRSA S1 S0 OTSV LOOP SI bit7 IM2 IM1 IM0 bit0 ITS 4 ITS 3 ITS 2 ITS 1 ITS 0
SW1
VI.8 - Connection Memory Data Register
CONTROL REGISTER (CTLR) bit15 SCR
After reset (0000)H
This 16 bit register is constituted by two 8 bit registers: SOURCE REGISTER (SRCR) and CONTROL REGISTER (CTLR). SOURCE REGISTER (SRCR) This register defines the source when this source is located on an Input Time Division Multiplex ITDMp: ITS 0/4 : Input time slot 0/4 define ITSx with: 0 x 31; IM0/2 : Input Time Division Multiplex 0/2 define ITDMp with: 0 p 7.
When D channels are multiplexed, see S0/S1 definition and tables here after.
37/130
STLC5466
CONTROL REGISTER (CTLR) defines each Output Time Slot OTSy of each Output Time Division Multiplex OTDMq: SI : SEQUENCE INTEGRITY SI = 1, the delay is always: (31 - ITSx) + 32 + OTSy (constant delay). SI = 0, the delay is minimum to pass through the data memory (variable delay).
LOOP: LOOPBACK per channel relevant if two connections has been established (bidirectional or not). LOOP = 1, OTSy, OTDMq is taken into account instead of ITSy, ITDMq. OTSV = 1, transparent Mode LOOPBACK. OTSV = 0, not Transparent Mode LOOPBACK. OTSV : OUTPUT TIME SLOT VALIDATED OTSV = 1, OTSy OTDMq is enabled. OTSV = 0, OTSy OTDMq is High impedance. (OTSy: Output Time slot with 0 y 31; OTDMq: Output Time Division Multiplex with 0 q 7). S1/S0 : Source
S1 0 0 1 1 S0 0 1 0 1 Source for each timeslot of DOUT0/7 Data Memory (Normal case) Connection Memory D channels from/to GCI multiplexes (See note and table hereafter) Pseudo Random Sequence Generator delivers sequences. Hyperchannel at n x 64 Kb/s is possible.
Note: * Connection When the source of D channels is selected (GCI channels defined by ITS 1/0) and when the destination is selected (Output timeslot defined by OTS 0/4; output TDM defined by OM 0/2) the upstream connection is set up; the downstream connection (reverse direction TDM to GCI) is set up automatically if ITS 2 bit is at 1. So BID, bit of CMAR must be written at"0". * Release Remember: write S1=1, S0=0 and ITS 2 bit = 0 to release the downstream connection; the upstream connection is released when the source changes.
38/130
STLC5466
Table: switching at 16 Kb/s when ITS3=0 S1 S0 ITS3 ITS2 ITSI ITS 0 Upstream Source: D channels of one GCI channel Destination: two bits of one TDM The contents of D channels of GCI 0 /3 of multiplex DIN4 are transferred into the output timeslot of one TDM defined by the destination register (CMAR). D channel of GCI 0 in bit 1/2 D channel of GCI 1 in bit 3/4 D channel of GCI 2 in bit 5/6 D channel of GCI 3 in bit 7/8 Downstream Source: two bits of one TDM Destination: D channels of one GCI channel The contents of the input times lot (same number as the number of the output timeslot) is transferred in D channel of GCI 0/3 of multiplex DOUT4 bit 1/2 in D channel of GCI 0 bit 3/4 in D channel of GCI 1 bit 5/6 in D channel of GCI 2 bit 7/8 in D channel of GCI 3 The contents of the input times lot (same number as the number of the output timeslot) is transferred in D channel of GCI 4/7 of multiplex DOUT4.
0
0
0
1
1
0
0
1
1
0
1
1
The contents of D channels of GCI 4/7 of multiplex DIN4 are transferred into the output timeslot of one TDM defined by the destination register (CMAR). D channel of GCI 4 in bit 1/2 bit 1/2 in D channel of GCI 4 D channel of GCI 5 in bit 3/4 bit 3/4 in D channel of GCI 5 D channel of GCI 6 in bit 5/6 bit 5/6 in D channel of GCI 6 D channel of GCI 7 in bit 7/8 bit 7/8 in D channel of GCI 7 The contents of D channels of The contents of the input times GCI 0 /3 of multiplex DIN5 are lot (same number as the transferred into the output times- number of the output timeslot) lot of one TDM defined by the is transferred in D channel of GCI 0/3 of multiplex DOUT5. destination register (CMAR). D channel of GCI 0 in bit 1/2 bit 1/2 in D channel of GCI 0 D channel of GCI 1 in bit 3/4 bit 3/4 in D channel of GCI 1 D channel of GCI 2 in bit 5/6 bit 5/6 in D channel of GCI 2 D channel of GCI 3 in bit 7/8 bit 7/8 in D channel of GCI 3 The contents of D channels of The contents of the input timesGCI 4/7 of multiplex DIN5 are lot (same number as the transferred into the output times- number of the output timeslot) lot of one TDM defined by the is transferred in D channel of GCI 4/7 of multiplex DOUT5. destination register (CMAR). D channel of GCI 4 in bit 1/2 bit 1/2 in D channel of GCI 4 D channel of GCI 5 in bit 3/4 bit 3/4 in D channel of GCI 5 D channel of GCI 6 in bit 5/6 bit 5/6 in D channel of GCI 6 D channel of GCI 7 in bit 7/8 bit 7/8 in D channel of GCI 7
39/130
STLC5466
Table: switching at 16 Kb/s when ITS3=1 S1 S0 ITS3 ITS2 ITSI ITS 0 Upstream Source: D channels of one GCI channel Destination: two bits of one TDM The contents of D channels of GCI 0 /3 of multiplex DIN4 are transferred into the output timeslot of one TDM defined by the destination register (CMAR). D channel of GCI 0 in bit 7/8 D channel of GCI 1 in bit 5/6 D channel of GCI 2 in bit 3/4 D channel of GCI 3 in bit 1/2 The contents of D channels of GCI 4/7 of multiplex DIN4 are transferred into the output timeslot of one TDM defined by the destination register (CMAR). D channel of GCI 4 in bit 7/8 D channel of GCI 5 in bit 5/6 D channel of GCI 6 in bit 3/4 D channel of GCI 7 in bit 1/2 The contents of D channels of GCI 0 /3 of multiplex DIN5 are transferred into the output timeslot of one TDM defined by the destination register (CMAR). D channel of GCI 0 in bit 7/8 D channel of GCI 1 in bit 5/6 D channel of GCI 2 in bit 3/4 D channel of GCI 3 in bit 1/2 The contents of D channels of GCI 4/7 of multiplex DIN5 are transferred into the output timeslot of one TDM defined by the destination register (CMAR). D channel of GCI 4 in bit 7/8 D channel of GCI 5 in bit 5/6 D channel of GCI 6 in bit 3/4 D channel of GCI 7 in bit 1/2 Downstream Source: two bits of one TDM Destination: D channels of one GCI channel The contents of the input times lot (same number as the number of the output timeslot) is transferred in D channel of GCI 0/3 of multiplex DOUT4 bit 7/8 in D channel of GCI 0 bit 5/6 in D channel of GCI 1 bit 3/4 in D channel of GCI 2 bit 1/2 in D channel of GCI 3 The contents of the input times lot (same number as the number of the output timeslot) is transferred in D channel of GCI 4/7 of multiplex DOUT4. bit 7/8 in D channel of GCI 4 bit 5/6 in D channel of GCI 5 bit 3/4 in D channel of GCI 6 bit 1/2 in D channel of GCI 7 The contents of the input times lot (same number as the number of the output timeslot) is transferred in D channel of GCI 0/3 of multiplex DOUT5. bit 7/8 in D channel of GCI 0 bit 5/6 in D channel of GCI 1 bit 3/4 in D channel of GCI 2 bit 1/2 in D channel of GCI 3 The contents of the input timeslot (same number as the number of the output timeslot) is transferred in D channel of GCI 4/7 of multiplex DOUT5. bit 7/8 in D channel of GCI 4 bit 5/6 in D channel of GCI 5 bit 3/4 in D channel of GCI 6 bit 1/2 in D channel of GCI 7
0
0
0
1
1
0
1
1
1
0
1
1
PRSA :S Pseudo Random Sequence analyser If PRSA = 1, PRS analyser is enabled during OTSy OTDMq and receives data: S0 = 0, data comes from Data Memory. S0 = 1 AND S1 = 1, Data comes from PRS Generator (Test Mode). If PRSA = 0, PRS analyser is disabled during OTSy OTDMq.
40/130
STLC5466
PS : Programmable Synchronization If PS = 1, Programmable Synchronization Signal Pin is at "1" during the bit time defined by OTSy and OTDMq. For OTSy and OTDMq with y = q = 0, PSS pin is at "1" during the first bit of the frame defined by the Frame synchronization Signal (FS). If PS = 0, PSS Pin is at "0" during the bit time defined by OTSy and OTDMq.
SCR : Scrambler/ Descrambler SCR=1, the scrambler or the descrambler are enabled. Both of them are located after the switching matrix. The scrambler is enabled when the output timeslot defined by the destination register (DSTR) is an output timeslot belonging to any TDM except the two GCI multiplexes; the contents of this output timeslot will be scrambled in accordance with the IUT-T V.29 Rec. The descrambler is enabled when the output timeslot defined by the destination register (DSTR) is an output timeslot belonging to the two GCI multiplexes except any TDM; the contents of this output timeslot is descrambled in accordance with the IUT-T V.29 Rec. Only 32 timeslots of 256 can be scrambled or/and descrambled: GCI side, only B1 and B2 can be selected in each GCI channel (16 GCI channels are available: 8 per GCI multiplex). *TDM side, it is forbidden to select a given timeslot more than once when several TDMs are selected. SCR=0, the scrambler or the descrambler are disabled; the contents of output timeslots are not modified. VI.9 - Connection Memory Address Register
ACCESS MODE REGISTER (AMR) bit15 Nu Nu TC CACL CAC BID CM bit8 bit7 OM1 READ OM2
CMAR (10)H
DESTINATION REGISTER (DSTR) bit0 OM0 OTS4 OTS3 OTS2 OTS1 OTS0
After reset (0800)H
This 16 bit register is constituted by two registers: DESTINATION REGISTER (DSTR) and ACCESS MODE REGISTER (AMR) respectively 8 bits and 6 bits. DESTINATION REGISTER (DSTR) Only when DSTR is written by the microprocessor, a memory access is launched. DSTR has two use modes depending on CM (bit of CMAR). CM = 1, access to connection memory (read or write); When CM = 1, OTS 0/4 and OM 0/2 bits are defined hereafter: OTS 0/4 : Output time slot 0/4 define OTSy with: 0 y 31; OM0/2 : Output Time Division Multiplex 0/2 define OTDMq with: 0 q 7. See table hereafter when DR04, DR24, DR44 and/or DR64 are at "1"; these bits of SMCR define the TDMs at 4 Mbit/s.
41/130
STLC5466
- The IM2/1 bits of Source Register (SRCR of CMDR) indicate the DIN pin number and the OM2/1 bits of Destination Register (DSTR of CMAR) indicate the Dout pin number
IM2 (bit7) 0 0 1 1 IM1 (bit6) 0 1 0 1 DIN pin DIN0 DIN2 DIN4 DIN6 OM2 (bit7) 0 0 1 1 OM1 (bit6) 0 1 0 1 DOUT pin DOUT0 DOUT2 DOUT4 DOUT6
- The ITS4/0 and IM0 bits of Source Register (SRCR of CMDR) indicate the input timeslot number. (IM0 bit is the Least Significant Bit; it indicates either even timeslot or odd timeslot.
ITS4 (bit4) 0 0 0 0 0 0 ITS3 (bit3) 0 0 0 0 0 0 ITS2 (bit2) 0 0 0 0 0 0 ITS1 (bit1) 0 0 0 0 1 1 ITS0 (bit0) 0 0 1 1 0 0 IM0 (bit5) 0 1 0 1 0 1 Input timeslot number 0 1 2 3 4 5
1
1
1
1
1
1
63
- The OTS4/0 and OM0 bits of Destination Register (DSTR of CMAR) indicate the output timeslot number. (OM0 bit is the Least Significant Bit; it indicates either even timeslot or odd timeslot.
OTS4 (bit4) 0 0 0 0 0 0 OTS3 (bit3) 0 0 0 0 0 0 OTS2 (bit2) 0 0 0 0 0 0 OTS1 (bit1) 0 0 0 0 1 1 OTS0 (bit0) 0 0 1 1 0 0 OM0 (bit5) 0 1 0 1 0 1 Output timeslot number 0 1 2 3 4 5
1
1
1
1
1
1
63
* Nota Bene: CLOCK A/B is at 4 or at 8 MHz in accordance with HCL bit of General Configuration Register GCR (02). - HCL=1, bit clock frequency is at 8 192 kHZ. For a TDM at 4 Mbit/s or 2Mbit/s, each received bit is sampled at 3/4 bit-time.
42/130
STLC5466
- HCL=0, bit clock frequency is at 4 096 kHz For a TDM at 4 Mbit/s, each received bit is sampled at half bit-time (at 4 Mbit/s, bit-time=244ns). For a TDM at 2 Mbit/s, each received bit is sampled at 3/4 bit-time (at 2 Mbit/s, bit-time=488ns). * Remarks: OM0, bit5 of DSTR indicates either even TDM or odd TDM if TDM at 2 Mb/s. OM0, bit5 of DSTR indicates either even Output timeslot or odd Output timeslot if TDM at 4 Mb/s. IM0, bit5 of SRCR indicates either even TDM or odd TDM if TDM at 2 Mb/s. IM0, bit5 of SRCR indicates either even Input timeslot or odd Input timeslot if TDM at 4 Mb/s.
43/130
STLC5466
ACCESS MODE REGISTER (AMR) READ : READ MEMORY READ = 1, Read Connection Memory (or Data Memory in accordance with CM). READ = 0, Write Connection Memory. CM : CONNECTION MEMORY CM = 1, Write or Read Connection Memory in accordance with READ. CM = 0, Read only Data Memory (READ = 0 has no effect). N.B. After software reset (bit 2 of IDCR Register) or pin reset the automate of the Connection Memory is launched. This automate initializes the Connection Memory within 250 microseconds at the most. This automate is stopped when the microprocessor writes (0200H) in CMAR Register (CM =1). : BIDIRECTIONNAL CONNECTION. BID = 1; Two connections are set up: * ITSx ITDMp ------> OTSy OTDMq (LOOP of CMDR Register is taken into account) and * ITSy ITDMq ------> OTSx OTDMp (LOOP of CMDR Register is not taken into account). BID = 0; One connection is set up: * ITSx ITDMp ------> OTSy OTDMq only. : CYCLICAL ACCESS CAC = 1 (BID is ignored) if Write Connection Memory, an automatic data write from Connection Memory Data Register (CMDR) up to 256 locations of Connection Memory occurs. The first address is indicated by the register DSTR, the last is (FF)H. if Read Connection Memory, an automatic transfer of data from the location indicated by the register (DSTR) into Connection Memory Data Register (CMDR) after reading by the microprocessor occurs. The last location is (FF)H. CAC = 0, Write and Read Connection Memory in the normal way.
BID
CAC
* N.B. After software reset (bit 2 of IDCR Register) or pin reset an automate is working to reset the connection memory (all "0"). The automate is stopped when the microprocessor writes TAAR Register with CAC= 0. CACL : CYCLICAL ACCESS LIMITED CACL = 1(BID is ignored) If Write Connection Memory, an automatic data write from Connection Memory Data Register (CMDR) up to 32 locations of Connection Memory occurs. The first location is indicated by OTS 0/4bits of the register (DSTR) related to OTDMq as defined by OM0/2 occurs. The last location is q +1 F(H). If Read Connection Memory, an automatic transfer of data from Connection Memory into Connection Memory Data Register (CMDR) after reading this last by the microprocessor occurs.The first location is indicated by OTS 0/4 bits of the register (DSTR) related to OTDMq as defined by OM0/2. The last location is q +1 F(H). CACL = 0, Write and Read Connection Memory in the normal way. TC : Transparent Connection TC = 1, (BID is ignored) if READ = 0: CAC = 0 and CACL = 0. The DSTR bits are taken into account instead of SRCR bits. SRCR bits are ignored (Destination and Source are identical). The contents of Input time slot i - Input multiplex j is switched into Output time slot i - Output multiplex j. CAC = 0 and CACL = 1. Up to 32 "Transparent Connections" are set up. CAC = 1 and CACL = 0. Up to 256 "Transparent Connections" are set up. TC = 0, Write and Read Connection Memory in accordance with BID.
44/130
STLC5466
VI.10 - Sequence Fault Counter Register
bit15 F15 F14 F13 F12 F11 F10 F9 bit8 F8 bit7 F7 F6 F5 F4 F3 F2 F1
SFCR (12)H
bit0 F0
After reset (0000)H
When this register is read by the microprocessor, this register is reset (0000)H. F0/15 : FAULT0/15 Number of faults detected by the Pseudo Random Sequence analyser if the analyser has been validated and has recovered the receive sequence. When the Fault Counter Register reaches (FFFF)H it stays at its maximum value.
* NB. As the SFCR is reset after reading, a 8-bit microprocessor must read the LSB that will represent the number of faults between 0 and 255. To avoid overflow escape notice, it is necessary to start counting at FF00h, by writing this value in SFCR before launching PRSA. If there are more than FFh errors, the SFCO interrupt bit (see interrupt register IR -38H address) will signal that the fault count register has reached the value FFFFh (because of the number of faults exeeded 255). VI.11 - Time Slot Assigner Address Register 1
bit15 TS4 TS3 TS2 TS1 TS0 READ Nu bit8 HDI bit7 r e s e r v e
TAAR1 (14)H
bit0 d
After reset (0100)H
READ
TS0/4 HDI
: READ MEMORY READ = 1, Read Time slot Assigner Memory 1. READ = 0, Write Time slot Assigner Memory 1. : TIME SLOTS0/4 These five bits define one of 32 time slots in which a channel is set-up or not. : HDLC1 INIT HDI = 1, TSA1 Memory, Tx HDLC1, Tx DMA1, Rx HDLC1, Rx DMA1 and GCI controllers are reset within 250 microseconds at the most. An automate writes data from Time slot Assigner Data Register1 (TADR1) (except CH0/4 bits) into each TSA Memory location. If the microprocessor reads Time slot Assigner Memory 1 after HDLC INIT, CH0/4 bits of Time slot Assigner Data Register are identical to TS0/4 bits of Time slot Assigner Address Register 1. HDI = 0, Normal state.
* N.B. After software reset (bit 2 of IDCR Register) or pin reset the automate above mentioned is working. The automate is stopped when the microprocessor writes TAAR Register with HDI = 0. VI.12 - Time Slot Assigner Data Register 1
bit15 V11 V10 V9 V8 V7 V6 V5 bit8 V4 bit7 V3 V2 V1 CH4 CH3 CH2 CH1
TADR1 (16)H
bit0 CH0
After reset (0000)H
CH0/4 V1/8
: CHANNEL0/4 These five bits define one of 32 channels associated to time slot defined by the previous Register 1(TAAR1). : VALIDATION The logical channel CHx is constituted by each subchannel 1 to 8 and validated by V1/8 bit at 1 respectively. V1 to V8 are at "0': the subchannels are ignored. V1 corresponds to the first bit received during the current time slot. V1 at 1: the first bit of the current time slot is taken into account in reception and in transmission the first bit transmitted is taken into account. V8 at 1: the last bit of the current time slot is taken into account in reception the last bit received and in transmission the last bit transmitted in transmission.
45/130
STLC5466
V9 : VALIDATION SUBCHANNEL V 9 = 1, each V1/8 bit is taken into account once every 250s. In transmit direction, data is transmitted consecutively during the time slot of the current frame and during the same time slot of the next frame.Id est.: the same data is transmitted in two consecutive frames. In receive direction, HDLC controller fetches data during the time slot of the current frame and ignores data during the same time slot of the next frame. V 9 = 0, each V1/8 bit is taken into account once every 125s. : DIRECT MHDLC ACCESS If V10 = 1, the Rx HDLC Controller 1 receives data issued from DIN8 input during the current time slot (bits validated by V1/8) and DOUT6 output transmits data issued from the Tx HDLC Controller. If V10 = 0, the Rx HDLC Controller1 receives data issued from the matrix output 7 during the current time slot; DOUT6 output delivers data issued from the matrix output 6 during the same current time slot. N.B: If D7 = 1, bit of General Configuration Register GCR1 the Tx HDLC controller1 is connected to matrix input 7 continuously so the HDLC frames can be sent to any DOUT (i.e. DOUT0 to DOUT7). : VALIDATION of CB pin This bit is not taken into account if CSMA = 1 (HDLC Transmit Command Register). if CSMA = 0: V11 = 1, Contention 1 Bus pin is validated and Echo 1 pin (which is an input) is not taken into account. V11 = 0, Contention Bus pin is high impedance during the current time slot (This pin is an open drain output). HTCR1 (18)H
bit8 CH3 CH2 CH1 CH0 READ Nu CF bit7 PEN CSMA NCRC F P1 P0 C1 bit0 C0
V10
V11
VI.13 - HDLC Transmit Command Register 1
bit15 CH4
After reset (0000)H
READ : READ COMMAND MEMORY READ = 1, READ COMMAND MEMORY. READ = 0, WRITE COMMAND MEMORY. CH0/4 : These five bits define one of 32 channels. C1/C0 : COMMAND BITS
C1 0 C0 0 Command Bits written by the microprocessor ABORT; if this command occurs during the current frame, HDLC Controller transmits seven "1" immediately, afterwards HDLC Controller transmits "1" or flag in accordance with F bit, generates an interrupt and waits new command such as START or CONTINUE. If this command occurs after transmitting a frame, HDLC Controller generates an interrupt and waits a new command such as START or CONTINUE. START; Tx DMA Controller is now going to transfer first frame from buffer related to initial descriptor. The initial descriptor address is provided by the Initiate Block located in external memory. CONTINUE; Tx DMA Controller is now going to transfer next frame from buffer related to next descriptor. The next descriptor address is provided by the previous descriptor from which the related frame had been already transmitted. HALT; after transmitting frame, HDLC Controller transmits "1" or flag in accordance with F bit, generates an interrupt and is waiting new command such as START or CONTINUE.
0
1
1
0
1
1
46/130
STLC5466
C1/C0 : STATUS BITS
C1 0 0 1 1 C0 0 1 0 1 STATUS BITS read by the microprocessor ABORT; the microprocessor has written ABORT or the transmitted frame has been aborted by the HDLC Controller and it waits new command such as START or CONTINUE. START; the microprocessor has written START.The HDLC Controller has not taken into account the command yet. CONTINUE; the HDLC Controller has taken into account the command START. TX DMA Controller is transferring frames. CONTINUE; Tx DMA Controller is now going to transfer next frame from buffer related to next descriptor. The next descriptor address is provided by the previous descriptor from which the related frame had been already transmitted.
P0/1
: PROTOCOL BITS
P1 0 0 1 1 P0 0 1 0 1 HDLC Transparent Mode 1 (one byte per timeslot); the fill character defined in FCR Register is taken into account. Transparent Mode 2 (one byte per timeslot); the fill character defined in FCR Register is not taken into account. Reserved Transmission Mode
F
: Flag F = 1; flags are transmitted between closing flag of current frame and opening flag of next frame. F = 0; "1" are transmitted between closing flag of current frame and opening flag of next frame.
NCRC : CRC NOT TRANSMITTED NCRC = 1, the CRC is not transmitted at the end of the frame. NCRC = 0, the CRC is transmitted at the end of the frame. CSMA : Carrier Sense Multiple Access with Contention Resolution CSMA = 1, CB1 output and the Echo Bit are taken into account during this channel transmission by the TxHDLC. CSMA = 0, CB output and the Echo Bit are defined by V11, bit of Time slot Assigner Data Register TADR1 (16)H. PEN : CSMA PENALTY significant if CSMA = 1 PEN = 1, the penalty value is 1; a transmitter which has transmitted a frame correctly will count (PRI +1) logic one received from Echo pin before transmitting next frame. (PRI, priority class 8 or 10 given by the buffer descriptor related to the frame. PEN = 0, the penalty value is 2; a transmitter which has transmitted a frame correctly will count (PRI +2) logic one received from Echo pin before transmitting next frame. (PRI, priority class 8 or 10 given by the transmit descriptor related to the frame). : Common flag CF = 1, the closing flag of previous frame and opening flag of next frame are identical if the next frame is ready to be transmitted. CF = 0, the closing flag of previous frame and opening flag of next frame are distinct.
CF
47/130
STLC5466
VI.14 - HDLC Receive Command Register 1
bit15 CH4 CH3 CH2 CH1 bit8 bit7 FM P1 P0 C1 CH0 READ AR21 AR20 AR11 AR10 CRC After reset (0000)H
HRCR1 (1A)H
bit0 C0
READ : READ COMMAND MEMORY READ = 1, READ COMMAND MEMORY. READ = 0, WRITE COMMAND MEMORY. CH0/4 : These five bits define one of 32 channels. C1/C0 : COMMAND BITS
C1 0 C0 0 Command Bits written by the microprocessor ABORT; if this command occurs during receiving a current frame, HDLC Controller stops the reception, generates an interrupt and waits new command such as START or CONTINUE. If this command occurs after receiving a frame, HDLC Controller generates an interrupt and waits a new command such as START or CONTINUE. START; Rx DMA Controller is now going to transfer first frame into buffer related to the initial descriptor. The initial descriptor address is provided by the Initiate Block located in external memory. CONTINUE; Rx DMA Controller is now going to transfer next frame into buffer related to next descriptor. The next descriptor address is provided by the previous descriptor from which the related frame had been already received. HALT; after receiving a frame, HDLC Controller stops the reception, generates an interrupt and waits a new command such as START or CONTINUE.
0
1
1
0
1
1
C1/C0 : STATUS BITS
C1 0 C0 0 Status Bits read by the microprocessor ABORT; the received current frame has been aborted (seven "1" at least have been received) or the microprocessor has written ABORT. The HDLC Controller waits a new command such as START or CONTINUE START; the microprocessor has written START.The HDLC Controller has not taken into account the command yet. CONTINUE; RX DMA Controller is transferring frames HALT; HDLC Controller stops the reception, generates an interrupt and waits a new command such as START or CONTINUE.
0 1 1
1 0 1
P0/1
: PROTOCOL BITS
P1 0 0 1 1 P0 0 1 0 1 HDLC Transparent Mode 1 (one byte per timeslot); the fill character defined in FCR Register is taken into account. Transparent Mode 2 (one byte per timeslot); the fill character defined in FCR Register is not taken into account. Reserved Transmission Mode
48/130
STLC5466
FM : Flag Monitoring This bit is a status bit read by the microprocessor. FM=1: HDLC Controller is receiving a frame or HDLC Controller has just received one flag. FM is put to 0 by the microprocessor. : CRC stored in external memory CRC = 1, the CRC is stored at the end of the frame in external memory. CRC = 0, the CRC is not stored into external memory. : Address Recognition10 AR10 = 1, First byte after opening flag of received frame is compared to AF0/7 bits of AFRDR. If the first byte received and AF0/7 bits are not identical the frame is ignored. AR10 = 0, First byte after opening flag of received frame is not compared to AF0/7 bits of AFRDR Register. : Address Recognition 11 AR11 = 1, First byte after opening flag of received frame is compared to all "1"s.If the first byte received is not all "1"s the frame is ignored. AR11 = 0, First byte after opening flag of received frame is not compared to all "1"s. : Address Recognition 20 AR20 = 1, Second byte after opening flag of received frame is compared to AF8/15 bits of AFRDR Register. If the second byte received and AF8/15 bits are not identical the frame is ignored. AR20 = 0, Second byte after opening flag of received frame is not compared to AF8/15 bits of AFRDR Register. : Address Recognition 21 AR21 = 1, Second byte after opening flag of received frame is compared to all "1"s. If the Second byte received is not all "1"s the frame is ignored. AR21 = 0, Second byte after opening flag of received frame is not compared to all "1"s.
CRC
AR10
AR11
AR20
AR21
Second Byte AR21 0 0 0 0 0 0 0 0 AR20 0 0 0 0 1 1 1 1
First Byte Conditions to Receive a Frame AR11 0 0 1 1 0 0 1 1 AR10 0 1 0 1 0 1 0 1 Each frame is received without condition. Only value of the first received byte must be equal to that of AF0/7 bits. Only value of the first received byte must be equal to all "1"s. The value of the first received byte must be equal either to that of AF0/7 or to all "1"s. Only value of the second received byte must be equal to that of AF8/15 bits. The value of the first received byte must be equal to that of AF0/7 bits and the value of the second received byte must be equal to that of AF8/15 bits. The value of first received byte is must be equal to all "1"s and the value of second received byte must be equal to that of AF8/15 bits. The value of the first received byte must be equal either to that of AF0/7 or to all "1"s and the value of the second received byte must be equal to that of AF8/15 bits. Only the value of the second received byte must be equal to all "1"s. The value of the first received byte must be equal to that of AF0/7 bits and the value of the second received byte must be equal to all "1"s.
1 1
0 0
0 0
0 1
49/130
STLC5466
Second Byte AR21 1 1 1 1 AR20 0 0 1 1
First Byte Conditions to Receive a Frame AR11 1 1 0 0 AR10 0 1 0 1 The value of the first received byte must be equal to all "1"s and the value of the second received byte must be equal to "1" also. The value of the first received byte must be equal either to that of AF0/7 or to "1" and the value of the second received byte must be equal to all "1"s. The value of the second received byte must be equal either to that of AF8/15 or to all "1"s. The value of the first received byte must be equal to that of AF0/7 bits and the value of the second received byte must be equal either to that of AF8/15 or to all "1"s. The value of the first received byte must be equal to "1" and the value of the second received byte must be equal either to that of AF8/15 or to all "1"s. The value of the first received byte must be equal either to that of AF0/7 or to "1" and the value of the second received byte must be equal either to that of AF8/15 or to all "1"s.
1 1
1 1
1 1
0 1
VI.15 - Address Field Recognition Address Register 1
bit15 CH4 CH3 CH2 CH1 CHO READ AMM bit8 Nu bit7 r e s e r v
AFRAR1 (1C)H
bit0 e d
After reset (0000)H
The write operation is launched when AFRAR is written by the microprocessor. AMM : Access to Mask Memory AMM=1, Access to Address Field Recognition Mask Memory. AMM=0, Access to Address Field Recognition Memory. READ : READ ADDRESS FIELD RECOGNITION MEMORY READ=1, READ AFR MEMORY. READ=0, WRITE AFR MEMORY. CH0/4 : These five bits define one of 32 channels in reception VI.16 - Address Field Recognition Data Register 1
bit15 bit8 bit7
AFRDR1 (1E)H
bit0
AF15/ AF14/ AF13/ AF12/ AF11/ AF10/ AF9/ AF8/ AF7/ AF6/ AF5/ AF4/ AF3/ AF2/ AF1/ AF0/ AFM15 AFM14 AFM13 AFM12 AFM11 AFM10 AFM9 AFM8 AFM7 AFM6 AFM5 AFM4 AFM3 AFM2 AFM1 AFM0 After reset (0000)H
AF0/15 : ADDRESS FIELD BITS AF0/7; First byte received; AF8/15: Second byte received. These two bytes are stored into Address Field Recognition Memory when AFRAR1 is written by the microprocessor.
AFM0/ 15 : ADDRESS FIELD BIT MASK0/15 if AMM=1 (AMM bit of AFRAR1) AMF0/7. When AR10=1 (See HRCR1) each bit of the first received byte is compared respectively to AFx bit if AFMx=0. In case of mismatching, the received frame is ignored. If AFMx=1, no comparison between AFx and the corresponding received bit. AMF8/15. When AR20=1 (See HRCR1) each bit of the second received byte is compared respectively to AFy bit if AFMy=0. In case of mismatching, the received frame is ignored. If AFMy=1, no comparison between AFy and the corresponding received bit. These two bytes are stored into Address Field Recognition Mask Memory when AFRAR 1 is written by the microprocessor (AMM=1).
50/130
STLC5466
VI.17 - Fill Character Register 1
bit15 r e s e r v e bit8 d bit7 FC7 FC6 FC5 FC4 FC3 FC2 FC1
FCR1 (20)H
bit0 FC0
After reset (0000)H
FC0/7
: FILL CHARACTER (eight bits) In Transparent Mode M1, two messages are separated by FILL CHARACTERS and the detection of one FILL CHARACTER marks the end of a message. GCIR0 (22)H
VI.18 - GCI Channels Definition Register 0 The definitions of x and y indices are the same for GCIR0, GCIR1, GCIR2, GCIR3: - 0 x 7, 1 of 8 GCI CHANNELS belonging to the same multiplex TDM4 or TDM5 - y = 0, TDM4 is selected - y = 1, TDM5 is selected.
bit15 TDM5 GCI CHANNEL 1 After reset (0000)H TDM4 bit8 bit7 TDM5 GCI CHANNEL 0
bit0 TDM4
ANA11 VCI11 V*11 VM11 ANA10 VCI10 V*10 VM10 ANA01 VCI01 V*01 VM01 ANA00 VCI00 V*00 VM00
VMxy
: VALIDATION of MONITOR CHANNELx, MULTIPLEX y: When this bit is at 1, monitor channel xy is validated. When this bit is at 0, monitor channel xy is not validated. On line to reset (if necessary) one MON channel which had been selected previously VMxy must be put at 0 during 125s before reselecting this channel. Deselecting one MON channel during 125s resets this MON channel. : VALIDATION of V Star x, MULTIPLEX y When this bit is at 1, V Star protocol is validated if VMxy=1. When this bit is at 0, GCI Monitor protocol is validated if VMxy=1. : VALIDATION of Command/Indicate CHANNEL x, MULTIPLEXy When this bit is at 1, Command/Indicate channel xy is validated. When this bit is at 0, Command/Indicate channel xy is not validated. It is necessary to let VCxy at "0" during 125 s to initiate the Command/Indicate channel.
V*xy
VCxy
ANAxy : ANALOG APPLICATION When this bit is at 1, Primitive has 6 bits if C/Ixy is validated. When this bit is at 0, Primitive has 4 bits if C/Ixy is validated. VI.19 - GCI Channels Definition Register 1
bit15 TDM5 GCI CHANNEL 3 After reset (0000)H TDM4 bit8 bit7 TDM5 GCI CHANNEL 4 TDM4
GCIR1 (24)H
bit0
ANA31 VCI31 V*31 VM31 ANA30 VCI30 V*30 VM30 ANA21 VCI21 V*21 VM21 ANA20 VCI20 V*20 VM20
For definition see GCI Channels Definition Register above.
51/130
STLC5466
VI.20 - GCI Channels Definition Register 2
bit15 TDM5 GCI CHANNEL 5 After reset (0000)H TDM4 bit8 bit7 TDM5 GCI CHANNEL 6 TDM4
GCIR2 (26)H
bit0
ANA51 VCI51 V*51 VM51 ANA50 VCI50 V*50 VM50 ANA41 VCI41 V*41 VM41 ANA40 VCI40 V*40 VM40
For definition see GCI Channels Definition Register above. VI.21 - GCI Channels Definition Register 3
bit15 TDM5 GCI CHANNEL 7 After reset (0000)H TDM4 bit8 bit7 TDM5 GCI CHANNEL 8 TDM4
GCIR3 (28)H
bit0
ANA71 VCI71 V*71 VM71 ANA70 VCI70 V*70 VM70 ANA61 VCI61 V*61 VM61 ANA60 VCI60 V*60 VM60
For definition see GCI Channels Definition Register above. VI.22 - Transmit Command / Indicate Register
bit15 D G0 CA2 CA1 CA0 READ 0 bit8 0 bit7 Nu Nu C6/A
TCIR (2A)H
bit0 C5/E C4/S1 C3S2 C2S3 C1S4
After reset (00FF)H
When this register is written by the microprocessor, these different bits mean: READ : READ C/I MEMORY READ = 1, READ C/I MEMORY. READ = 0, WRITE C/I MEMORY.
CA 0/2 : TRANSMIT COMMAND/INDICATE MEMORY ADDRESS CA0/2: These bits define one of eight Command/Indicate Channels. G0 : This bit defines one of two GCI multiplexes. G0 = 0, TDM4 is selected. G0 = 1, TDM5 is selected. : New Primitive to be transmitted C6 is transmitted first if ANA = 1. C4 is transmitted first if ANA = 0. : Destination; this bit defines the destination of bit 0 to 5. D=0: the primitive C6 to C1 is transmitted directly into GCI channel defined by G0 and CA 0/2 D=1: the 6 bit word A, E, S1, S2, S3, S4 is put instead of the six bits received latest during the timeslot 4n+3 (GCI channel defined by G0 and CA 0/2) and transmitted into any selected output timeslot after switching.
bit8 G0 G0 CA2 CA2 CA1 CA1 CA0 READ CA0 READ 0 0 0 0 bit7 Nu Nu C6 A C5 E C4 S1 C3 S2 C2 S3 bit0 C1 S4
C6/1
D
bit15 D=0 D=1
C6/1
: New Primitive to be transmitted to the selected GCI channel (DOUT4 or DOUT5) New 6 bit word to be transmitted into any output timeslot.
A, E, : S1 to S4
52/130
STLC5466
The New Primitive is taken into account by the transmitter after writing bits 8 to 15 (if 8bit microprocessor). Transmit Command/Indicate Register (after reading)
bit15 D=0 D=1 G0 G0 CA2 CA2 CA1 CA1 CA0 READ CA0 READ Nu Nu bit8 Nu Nu bit7 PT1 PT1 PT0 PT0 C6 A C5 E C4 S1 C3 S2 C2 S3 bit0 C1 S4
When this register is read by the microprocessor, these different bits mean: READ : READ C/I MEMORY READ = 1, READ C/I MEMORY. READ = 0, WRITE C/I MEMORY.
CA 0/2 : TRANSMIT C/I ADDRESS CA0/2: These bits define one of eight Command/Indicate Channels. G0 : This bit defines one of two GCI multiplexes. G0 = 0, TDM4 is selected. G0 = 1, TDM5 is selected. : Destination. This bit defines the destination of bits 0 to 5. D=0: the destination is a GCI channel defined by G0 and CA0/2. D=1:the destination is any TDM (after switching). : Last Primitive transmitted. Case of D=0
D
C6/1
A, E, : 6 bit word transmitted. Case of D=1. S1 to S4 PT0/1 : Status bits
P1 0 0 1 1 P0 0 1 0 1 Primitive Status Primitive has not been transmitted yet. Primitive has been transmitted once. Primitive has been transmitted twice. Primitive has been transmitted three times or more.
VI.23 - Transmit Monitor Address Register
bit15 0 G0 MA2 MA1 MA0 READ Nu bit8 Nu bit7 Nu Nu TIV FABT L NOB
TMAR (2C)H
bit0 0 Nu
After reset (000F)H
When this register is written by the microprocessor, these different bits mean: READ : READ MON MEMORY READ=1, READ MON MEMORY. READ=0, WRITE MON MEMORY.
MA 0/2 : TRANSMIT MONITOR ADDRESS MA 0/2:These bits define one of eight Monitor Channel if validated. G0 : This bit defines one of two GCI multiplexes. G0 = 0, TDM4 is selected. G0 = 1, TDM5 is selected. : NUMBER OF BYTE to be transmitted NOB = 1, One byte to transmit. NOB = 0, Two bytes to transmit.
NOB
53/130
STLC5466
L : Last byte L = 1, the word (or the byte) located in the Transmit Monitor Data Register (TMDR) is the last. L = 0, the word (or the byte) located in the Transmit Monitor Data Register (TMDR) is not the last. : FABT = 1, the current message is aborted by the transmitter. : Timer interrupt is Validated TIV = 1, Time Out alarm generates an interrupt when the timer has expired. TIV = 0, Time Out alarm is masked.
FABT TIV
If 8 bit microprocessor the Data (TMDR Register) is taken into account by the transmitter after writing bits 8 to 15 of this register. Transmit Monitor Address Register (after reading)
bit15 0 G0 MA2 MA1 MA0 READ Nu bit8 Nu bit7 Nu Nu TO ABT L NOBT EXE bit0 IDLE
When this register is read by the microprocessor, these different bits mean: READ, MA0/2, G0 have same definition as already described for the write register cycle. IDLE EXE : When this bit is at "1", IDLE (all 1's) is transmitted during the channel validation. : EXECUTED When this status bit is at "1", the command written previously by the microprocessor has been executed and a new word can be stored in the Transmit Monitor Data Register (TMDR) by the microprocessor. When this bit is at "0", the command written previously by the microprocessor has not yet been executed. : NUMBER OF BYTE which has been transmitted. NOBT = 1, the first byte is transmitting. NOB T = 0, the second byte is transmitting, the first byte has been transmitted. : Last byte, this bit is the L bit which has been written by the microprocessor. : ABORT ABT=1, the remote receiver has aborted the current message. : Time Out one millisecond TO = 1, the remote receiver has not acknowledged the byte which has been transmitted one millisecond ago. TMDR (2E)H
bit8 M17 M16 M15 M14 M13 M12 M11 bit7 M08 M07 M06 M05 M04 M03 M02 bit0 M01
NOBT
L ABT TO
VI.24 - Transmit Monitor Data Register
bit15 M18
After reset (FFFF)H
M08/01 : First Monitor Byte to transmit. M08 bit is transmitted first. M18/11 : Second Monitor Byte to transmit if NOB = 0 (bit of TMAR). M18 bit is transmitted first.
54/130
STLC5466
VI.25 - Transmit Monitor Interrupt Register
bit15 MI71 MI61 MI51 TDM5 MI41 MI31 MI21 MI11 bit8 MI01 bit7 MI70 MI60 MI50 TDM4 MI40 MI30 MI20 MI10
TMIR (30)H
bit0 MI00
After reset (0000)H
When the microprocessor read this register, this register is reset (0000)H. MIxy : Transmit Monitor Channel x Interrupt, Multiplex y with: 0 x 7, 1 of 8 GCI CHANNELS belonging to the same multiplex TDM4 or TDM5 y = 0, GCI CHANNEL belongs to the multiplex TDM4 and y = 1 to TDM5. MIxy = 1 when: - a word has been transmitted and pre-acknowledged by the Transmit Monitor Channel xy (In this case the Transmit Monitor Data Register (TMDR) is available to transmit a new word) or - the message has been aborted by the remote receive Monitor Channel or - the Timer has reached one millisecond (in accordance with TIV bit of TMAR) by IM3 bit of IMR. When MIxy goes to "1", the Interrupt MTX bit of IR is generated. Interrupt MTX can be masked. VI.26 - Memory Interface Configuration Register
bit15 P41 P40 P31 P30 P21 P20 P11 bit8 P10 bit7 Nu Nu Nu Nu Nu Nu Nu
MICR (32)H
bit0 REF
After reset (0000)H
REF
:
MEMORY REFRESH REF=1, SDRAM REFRESH is validated REF=0, SDRAM REFRESH is not validated E0/1 E0/1 E0/1 E0/1
P1 E0/1 PRIORITY 1 for entity defined by P2 E0/1 PRIORITY 2 for entity defined by P3 E0/1 P4 E0/1 PRIORITY 3 for entity defined by PRIORITY 4 for entity defined by Entity definition:
E1 0 0 1 1 E0 0 1 0 1
Entity Rx DMA Controller Microprocessor Tx DMA Controller Interrupt Controller
PRIORITY 5 is the last priority for SDRAM Refresh if validated. SDRAM Refresh obtains PRIORITY 0 (the first priority) automatically when the first half cycle is spend without access to memory. After reset (E400)H, the Rx DMA Controller has the PRIORITY 1 the Microprocessor has the PRIORITY 2 the Tx DMA Controller has the PRIORITY 3 the Interrupt Controller has the PRIORITY 4
55/130
STLC5466
VI.27 - Initiate Block Address Register 1
bit15 A23 A22 A21 A20 A19 A18 A17 bit8 A16 bit7 A15 A14 A13 A12 A11 A10 A9
IBAR1 (34)H
bit0 A8
After reset (0000)H
A8/23 : Address bits. These 16 bits are the segment address bits of the Initiate Block (A8 to A23 for the external memory).The offset is zero (A0 to A7 ="0"). This register concerns the first 32 HDLC Controller 1 named HDLC 1 connected to Din7/Dout7 of the switching matrix. The Interrupt Queue is common for the first HDLC Controller1 and for the second HDLC Controller 2. So this register concerns the location of the Interrupt Queue. The location of the Interrupt Queue is found from the contents of this first IBAR Register 1 (34)H. A8/23 : Address bits. These 16 bits are the segment address bits of the Initiate Block (A8 to A23 for the external memory in the MHDLC address space).The offset is zero (A0 to A7 ="0"). The Initiate Block Address (IBA1) is:
23 A23 A22 A21 A20 A19 A18 A17 A16 A15 A14 A13 A12 A11 A10 A9 8 A8 7 0 0 0 0 0 0 0 0 0
The 23 more significant bits define one of 8 Megawords. (One word comprises two bytes.) The least significant bit defines one of two bytes when the microprocessor selects one byte. Example: MHDLC device address inside P mapping = 100000H Initiate Block for HDLC1 address inside P mapping = 110000H IBAR1 value = (110000 - 100000)/256 = 100H VI.28 - Interrupt Queue Size Register
bit15 TBFS 0 0 0 0 0 0 bit8 0 bit7 HS2 HS1 HS0 MS2 MS1 MS0 CS1
IQSR(36)H
bit0 CS0
After reset (0000)H
CS0/1 : Command/Indicate Interrupt Queue Size These two bits define the size of Command/Indicate Interrupt Queue in external memory. The location is IBA + 256 + HDLC Queue size + Monitor Channel Queue Size (see The Initiate Block Address (IBA)). MS0/2 : Monitor Channel Interrupt Queue Size These three bits define the size of Monitor Channel Interrupt Queue in external memory. The location is IBA + 256 + HDLC Queue size.
56/130
STLC5466
HS0/2 : HDLC Interrupt Queue Size These three bits define the size of HDLC status Interrupt Queue in external memory for each channel. The location is IBA+256 (see The Initiate Block Address (IBA))
HS2 0 0 0 0 1 1 1 1 HS1 0 0 1 1 0 0 1 1 HS0 0 1 0 1 0 1 0 1 HDLC Queue Size 128 words 256 word 384 words 512 words 640 words 768 words 896 words 1024 words MS2 0 0 0 0 1 1 1 1 MS1 0 0 1 1 0 0 1 1 MS0 0 1 0 1 0 1 0 1 MON Queue Size 128 words 256 word 384 words 512 words 640 words 768 words 896 words 1024 words CS1 0 0 1 1 CS0 0 1 0 1 C/I Queue Size 64 words 128 words 192 words 256 words
TBFS : Time Base running with Frame Synchronisation signal TBFS=1, the Time Base defined by the Timer Register (see page 84) is running on the rising edge of Frame Synchronisation signal. TBFS=0, the Time Base defined by the Timer Register is running on the rising edge of MCLK signal. VI.29 - Interrupt Register
bit15 Nu Nu SFCO PRSR TIM bit8 bit7
IR (38)H
bit0 INT INT Tx Tx Rx Rx ICOV MTX MRX C/IRX HDLC FOV FWAR FOV FWAR FOV FWAR After reset (0000)H
This register is read only. When this register is read by the microprocessor, this register is reset (0000). If not masked, each bit at "1" generates "1" on INT0 pin. Bit 0 and bit 5 to 10 are common to 64 HDLC controllers. HDLC : HDLC INTERRUPT HDLC = 1, Tx HDLC or Rx HDLC has generated an interrupt The status is in the HDLC queue. : Command/Indicate Rx Interrupt C/IRX = 1, Rx Command/Indicate has generated an interrupt. The status is in the HDLC queue. : Rx MONITOR CHANNEL INTERRUPT MRX = 1, one Rx MONITOR CHANNEL has generated an interrupt. The status is in the Rx Monitor Channel queue : Tx MONITOR CHANNEL INTERRUPT MTX = 1, one or several Tx MONITOR CHANNELS have generated an interrupt. Transmit Monitor Interrupt Register (TMIR) indicates the Tx Monitor Channels which have generated this interrupt. : INTERRUPT CIRCULAR OVERLOAD ICOV = 1, One of three circular interrupt memories is completed.
C/IRX
MRX
MTX
ICOV
57/130
STLC5466
RxFWAR : Rx DMA CONTROLLER FIFO WARNING RxFWAR = 1, Rx DMA CONTROLLER has generated an interrupt, its fifo is 3/4 completed. RxFOV : Rx DMA CONTROLLER FIFO OVERLOAD RxFOV = 1, Rx DMA CONTROLLER has generated an interrupt, it cannot transfer data from Rx HDLC to external memory, its fifo is completed.
TxFWAR : Tx DMA CONTROLLER FIFO WARNING TxFWAR = 1, Tx DMA CONTROLLER has generated an interrupt, its fifo is 3/4 completed. TxFOV : Tx DMA CONTROLLER FIFO OVERLOAD TxFOV = 1, Tx DMA CONTROLLER has generated an interrupt, it cannot transfer data from Tx HDLC to external memory, its fifo is completed.
INTFWAR: INTERRUPT CONTROLLER FIFO WARNING INTFWAR = 1, INTERRUPT CONTROLLER has generated an interrupt, its fifo is 3/4 completed. INTFOV : INTERRUPT CONTROLLER FIFO OVERLOAD INTFOV = 1, INTERRUPT CONTROLLER has generated an interrupt, it cannot transfer status from DMA and GCI controllers to external memory, its internal fifo is completed. TIM PRSR : TIMER TIM = 1, the programmable timer has generated an interrupt. : Pseudo Random Sequence Recovered PRSR = 1,the Pseudo Random Sequence transmitted by the generator has been recovered by the analyser. : Sequence Fault Counter Overload SFCO = 1, the Fault Counter has reached the value FFFF(H). IMR (3A)H
bit8 Nu IM13 IM12 IM11 IM10 IM9 IM8 bit7 IM7 IM6 IM5 IM4 IM3 IM2 IM1 bit0 IM0
SFCO
VI.30 - Interrupt Mask Register
bit15 Nu
After reset (FFFF)H
IM13/0 : INTERRUPT MASK 0/7 When IM0 = 1, HDLC bit is masked. When IM1 =1, C/IRX bit is masked. When IM2 = 1, MRX bit is masked. When IM3 = 1, MTX bit is masked. When IM4 = 1, ICOV bit is masked When IM5 = 1, RxFWAR bit is masked. When IM6 = 1, RxFOV bit is masked. When IM7 = 1, TxFWAR bit is masked. When IM8 = 1, TxFOV bit is masked. When IM9 = 1, INTFWAR bit is masked. When IM10 = 1, INTFOV bit is masked. When IM11 = 1, TIM bit is masked. When IM12 = 1, PRSR bit is masked. When IM13 = 1, SFCO bit is masked.
58/130
STLC5466
VI.31 - Timer Register 1
bit15 S3 S2 S1 S0 MS9 MS8 MS7 0 to 5s bit8 MS6 bit7 MS5 MS4 MS3 MS2 MS1 MS0 MM1 0 to 999ms After reset (0800)H
TIMR1 (3C)H
bit0 MM0 0 to 3x0.25ms
This programmable register indicates the time at the end of which the Watch Dog delivers logic "1" on the pin WDO (which is an output) but only if the microprocessor does not reset the counter assigned (with the help of WDR bit of IDCR (Identification and Dynamic Command Register) during the time defined by the Timer Register.When the microprocessor does not reset the counter, the pin WDO delivers logic "1 as soon as delta T plus programmed time are reached. (delta T from one to two clock periods of the associated counter). Remark: the time indicated in this register is obtained when the clock period of the associated counter is 250 microseconds. The minimum programmable time is four clock periods (1 millisecond in this case); the duration of the pulse delivered by the pin WDO is one clock period (250 microseconds). The Timer Register and its counter can be used as a time base by the microprocessor. An interrupt (TIM) is generated at each period defined by the Timer Register if the microprocessor does not reset the counter. To reset the counter, WDR (bit of IDCR) must be set to "1" by the microprocessor. The Watch Dog or the Timer is incremented by the Frame Synchronisation clock divided by two (TBFS=1) or by a submultiple of MCLK signal (TBFS=0; TBFS, bit of Interrupt Queue Size Register). Example: TBFS=1 if the Frame Synchronisation clock is at 8 kHz, the period of the counter clock is 250 microseconds TBFS=0 if MCLK clock is at 32768 kHz the clock period of the counter is 250 microseconds (inverse of 32768kHz divided by 8192). When TSV=1{bit of General Configuration Register)} this programmable register (TIMR1) is not significant. VI.32 - Test Register
bit15 r e s e r v e bit8 d bit7 r e s e r v e
TR (3E)H
bit0 d
T15/0 : Test bits 0/15 These bits are reserved for the test of the circuit in production.The use of these bits is forbidden.
59/130
STLC5466
VI.33 - General Configuration Register 2
bit15 Nu Nu Nu Nu Nu Nu Nu bit8 Nu bit7 Nu SWAP D6 BYP NINIT 0 MC1
GCR2 (42)H
bit0 MC0
After reset (0000)H id 512ms
MC0/1 :
Master Clock0/1 MC0/1: these two bits take into account the signal applied on MCLK pin. So whatever the frequency may be, the internal circuit operates with the appropriate internal clock and the exchanges between Multi-HDLC and SDRAM are at the Master Clock frequency.
MC1 0 0 1 1 MC0 0 1 0 1 Signal applied on MCLK pin 66MHz 50MHz 33MHz Not used Exchanges between Multi-HDLC and SDRAM with common clock at 66MHz 50MHz 33MHz Not used
The duration of the pulse named token ring is equal to the period of master clock applied to MCLK pin. NINIT : NOT INIT NINIT=1; when the microprocessor writes the SDRAM register with NINIT=1, the SDRAM will not be initialized. NINIT=0; when the microprocessor writes the SDRAMR register with NINIT=0, the SDRAM will be initialized in accordance with LT0/2 bits (of SDRAMR). In case of several Multi-HDLC's connected to the same memory, only one of them initializes and refreshes the SDRAM. So the GCR2 registers of these Multi-HDLC's are same contents except this bit which initializes the SDRAM. BYP : BYPASS BYPASS=1; the write FIFO and the read fetch memory located in the microprocessor interface are bypassed. BYPASS=0; the write FIFO and the read fetch memory located in the microprocessor interface are used when the microprocessor accesses the shared memory. : HDLC2 connected to MATRIX D6=1, the transmit HDLC2 is connected to matrix input 6, the DIN6 signal is ignored.
D6
60/130
STLC5466
SWAP SWAP=1 The first byte (named 2b) of frames received (or transmitted) by the HDLCs is stored in bit 8/15 of the shared memory (or located in bit 8/15); the first bit received is stored in bit 8 of the shared memory. The first bit to be transmitted is located in bit 8 of the shared memory. The second byte (named 2b+1) of the frame received (or transmitted) by the HDLCs is stored in bit 0/7 of the shared memory; the first bit of the second byte received is stored in bit 0 of the shared memory. The ninth bit to be transmitted is located in bit 0 of the shared memory. The bytes named (2b) are located in bit 8/15 of the shared memory; b from 0 to 2047. The bytes named (2b+1) are located in bit 0/7of the shared memory. SWAP=0 The first byte (named 2b) of frames received (or transmitted) by the HDLCs is stored in bit 0/7 of the shared memory (or located in bit 0/7); the first bit received is stored in bit 0 of the shared memory. The first bit to be transmitted is located in bit 0 of the shared memory. The second byte (named 2b+1) of the frame received (or transmitted) by the HDLCs is stored in bit 8/15 of the shared memory; the first bit of the second received is stored in bit 8 of the shared memory. The ninth bit to be transmitted is located in bit 8 of the shared memory. The bytes named (2b) are located in bit 0/7 of the shared memory; b from 0 to 2047 The bytes named (2b+1) are located in bit 8/15 of the shared memory. SFMR (4E)H
bit8 A22 A21 A20 A19 A18 A17 A16 bit7 Nu Nu Nu Nu Nu Nu NAB bit0 FFA
VI.34 - Split Fetch Memory Register
bit15 A23
After reset (0000)H
This register must be programmed after reset before the first SDRAM access. Writing register is forbidden between two SDRAM accesses. FFA : Fast Fetch memory Access. This bit is taken into account only when synchronous 386EX microprocessor is selected. FFA = 1; in case of read from synchronous 386EX microprocessor * if LBA delivered by the microprocessor is at"1", * if the word is already in the Fetch memory, * if the Write FIFO is empty, * if no current burst due to a previous read Access then there is no Twait. FFA = 0; in case of read from synchronous 386EX microprocessor with the same conditions described above there is one Twait. : No Anticipation Burst NAB = 1. A read burst is generated only when a word required by the microprocessor is not present in the fetch memory. No anticipation is done for potential further accesses. NAB = 0. An anticipation is added to the fetch memory management. If one of four words of a burst is read by the microprocessor in the fetch memory and if the following four words are not present and valid in the fetch memory, then the following four words are transferred automatically by anticipation from SDRAM to the fetch memory.
61/130
NAB
STLC5466
A16/23: These 8 bits define two areas of the shared Memory; each area is multiple of 64Kbytes. The shared Memory is split in two parts: the upper part of the shared Memory is affected to the first half part of the Fetch Memory located in the microprocessor interface, the lower part is affected to the second half part of the Fetch Memory. Particular case: A16/23=0. One area of the shared Memory is defined, the two parts of the Fetch Memory are merged. VI.35 - Time Slot Assigner Address Register 2
bit15 TS4 TS3 TS2 TS1 TS0 READ Nu bit8 HDI bit7 r e s e r v e
TAAR2 (54)H
bit0 d
After reset (0100)H
This register concerns the second 32 HDLC controller named HDLC2 connected to input6/output6 of the switching matrix. READ : READ MEMORY READ = 1, Read Time slot Assigner Memory 2. READ = 0, Write Time slot Assigner Memory 2. : TIME SLOTS0/4 These five bits define one of 32 time slots in which a channel is set-up or not. : HDLC2 INIT HDI = 1, TSA2 Memory, Tx HDLC2, Tx DMA2, Rx HDLC2, Rx DMA2 are reset. An automate writes data from Time slot Assigner Data Register 2 (TADR2) (except CH0/4 bits) into each TSA Memory location. If the microprocessor reads Time slot Assigner Memory 2 after HDLC2 INIT, CH0/4 bits of Time slot Assigner Data Register are identical to TS0/4 bits of Time slot Assigner Address Register 2. HDI = 0, Normal state.
TS0/4 HDI
* N.B. After software reset (bit 2 of IDCR Register) or pin reset the automate above mentioned is working. The automate is stopped when the microprocessor writes TAAR Register with HDI = 0. VI.36 - Time Slot Assigner Data Register 2
bit15 V11 V10 V9 V8 V7 V6 V5 bit8 V4 bit7 V3 V2 V1 CH4 CH3 CH2 CH1
TADR2 (56)H
bit0 CH0
After reset (0000)H
This register concerns the second 32 HDLC controller named HDLC2 connected to input6/output6 of the switching matrix CH0/4 : CHANNEL0/4 These five bits define one of 32 channels associated to time slot defined by the previous Register 2(TAAR2). : VALIDATION The logical channel CHx is constituted by each subchannel 1 to 8 and validated by V1/8 bit at 1 respectively. V1 to V8 are at "0': the subchannels are ignored. V1 corresponds to the first bit received during the current time slot. V1 at 1: the first bit of the current time slot is taken into account in reception and in transmission the first bit transmitted is taken into account. V8 at 1: the last bit of the current time slot is taken into account in reception the last bit received and in transmission the last bit transmitted in transmission.
V1/8
62/130
STLC5466
V9 : VALIDATION SUBCHANNEL V 9 = 1, each V1/8 bit is taken into account once every 250s. In transmit direction, data is transmitted consecutively during the time slot of the current frame and during the same time slot of the next frame.Id est.: the same data is transmitted in two consecutive frames. In receive direction, HDLC controller fetches data during the time slot of the current frame and ignores data during the same time slot of the next frame. V 9 = 0, each V1/8 bit is taken into account once every 125s. : DIRECT MHDLC ACCESS If V10 = 1, the Rx HDLC Controller 2 receives data issued from DIN9 input during the current time slot (bits validated by V1/8) and DOUT7 output transmits data issued from the Tx HDLC Controller 2. If V10 = 0, the Rx HDLC Controller2 receives data issued from the matrix output 6 during the current time slot; DOUT7 output delivers data issued from the matrix output 7 during the same current time slot. N.B: If D6 = 1, bit of General Configuration Register GCR2, the Tx HDLC controller 2 is connected to matrix input 6 continuously so the HDLC frames can be sent to any DOUT (i.e. DOUT0 to DOUT7) from the TX HDLC Controller2. : VALIDATION of CB2 pin This bit is not taken into account if CSMA = 1 (HDLC Transmit Command Register 2). if CSMA = 0: V11 = 1, Contention Bus 2 pin is validated and Echo 2 pin (which is an input) is not taken into account. V11 = 0, Contention Bus 2 pin is high impedance during the current time slot (This pin is an open drain output). HTCR2 (58)H
bit8 CH3 CH2 CH1 CH0 READ Nu CF bit7 PEN CSMA NCRC F P1 P0 C1 bit0 C0
V10
V11
VI.37 - HDLC Transmit Command Register 2
bit15 CH4
After reset (0000)H
READ : READ COMMAND MEMORY READ = 1, READ COMMAND MEMORY. READ = 0, WRITE COMMAND MEMORY. CH0/4 : These five bits define one of 32 channels of the second 32 HDLC controller named HDLC 2 connected to input6/output6 of the switching matrix. C1/C0 : COMMAND BITS
C1 0 C0 0 Command Bits ABORT; if this command occurs during the current frame, HDLC Controller transmits seven "1" immediately, afterwards HDLC Controller transmits "1" or flag in accordance with F bit, generates an interrupt and waits new command such as START or CONTINUE. If this command occurs after transmitting a frame, HDLC Controller generates an interrupt and waits a new command such as START or CONTINUE. START; Tx DMA Controller is now going to transfer first frame from buffer related to initial descriptor. The initial descriptor address is provided by the Initiate Block located in external memory. CONTINUE; Tx DMA Controller is now going to transfer next frame from buffer related to next descriptor. The next descriptor address is provided by the previous descriptor from which the related frame had been already transmitted. HALT; after transmitting frame, HDLC Controller transmits "1" or flag in accordance with F bit, generates an interrupt and is waiting new command such as START or CONTINUE.
0
1
1
0
1
1
63/130
STLC5466
C1/C0 : STATUS BITS
C1 0 0 1 1 C0 0 1 0 1 STATUS BITS read by the microprocessor ABORT; the microprocessor has written ABORT or the transmitted frame has been aborted by the HDLC Controller2 and it waits new command such as START or CONTINUE. START; the microprocessor has written START.The HDLC Controller2 has not taken into account the command yet. CONTINUE; the HDLC Controller2 has taken into account the command START. TX DMA Controller is transferring frames. CONTINUE; Tx DMA Controller is now going to transfer next frame from buffer related to next descriptor. The next descriptor address is provided by the previous descriptor from which the related frame had been already transmitted.
P0/1
: PROTOCOL BITS
P1 0 0 1 1 P0 0 1 0 1 HDLC Transparent Mode 1 (one byte per timeslot); the fill character defined in FCR Register is taken into account. Transparent Mode 2 (one byte per timeslot); the fill character defined in FCR Register is not taken into account. Reserved Transmission Mode
F
: Flag F = 1; flags are transmitted between closing flag of current frame and opening flag of next frame. F = 0; "1" are transmitted between closing flag of current frame and opening flag of next frame.
NCRC : CRC NOT TRANSMITTED NCRC = 1, the CRC is not transmitted at the end of the frame. NCRC =0, the CRC is transmitted at the end of the frame. CSMA : Carrier Sense Multiple Access with Contention Resolution CSMA = 1, CB2 output and the Echo Bit EC2 are taken into account during this channel transmission by the TxHDLC2. CSMA = 0, CB2 output and the Echo Bit EC2 are defined by V11 (see "Time slot Assigner Data Register 2 TADR2(56)H"). PEN : CSMA PENALTY significant if CSMA = 1 PEN = 1, the penalty value is 1; a transmitter which has transmitted a frame correctly will count (PRI +1) logic one received from Echo pin before transmitting next frame. (PRI, priority class 8 or 10 given by the buffer descriptor related to the frame. PEN = 0, the penalty value is 2; a transmitter which has transmitted a frame correctly will count (PRI +2) logic one received from Echo pin before transmitting next frame. (PRI, priority class 8 or 10 given by the transmit descriptor related to the frame). : Common flag CF = 1, the closing flag of previous frame and opening flag of next frame are identical if the next frame is ready to be transmitted. CF = 0, the closing flag of previous frame and opening flag of next frame are distinct. HRCR2 (5A)H
bit8 CH3 CH2 CH1 bit7 FM P1 P0 C1 bit0 C0
CF
VI.38 - HDLC Receive Command Register 2
bit15 CH4 CH0 READ AR21 AR20 AR11 AR10 CRC After reset (0000)H
64/130
STLC5466
READ : READ COMMAND MEMORY READ = 1, READ COMMAND MEMORY. READ = 0, WRITE COMMAND MEMORY. CH0/4 : These five bits define one of 32 channels of the second 32 HDLC Controller2 named HDLC controller2 connected to Iinput6/output6 of the switching matrix C1/C0 : COMMAND
C1 0 C0 0 Command Bits ABORT; if this command occurs during receiving a current frame, HDLC Controller stops the reception, generates an interrupt and waits new command such as START or CONTINUE. If this command occurs after receiving a frame, HDLC Controller generates an interrupt and waits a new command such as START or CONTINUE. START; Rx DMA Controller is now going to transfer first frame into buffer related to the initial descriptor. The initial descriptor address is provided by the Initiate Block located in external memory. CONTINUE; Rx DMA Controller is now going to transfer next frame into buffer related to next descriptor. The next descriptor address is provided by the previous descriptor from which the related frame had been already received. HALT; after receiving a frame, HDLC Controller stops the reception, generates an interrupt and waits a new command such as START or CONTINUE.
0
1
1
0
1
1
C1/C0 :
STATUS BITS
C1 0 C0 0 Status Bits read by the microprocessor ABORT; the received current frame has been aborted (seven "1" at least have been received) or the microprocessor has written ABORT. The HDLC Controller2 waits a new command such as START or CONTINUE START; the microprocessor has written START.The HDLC Controller2 has not taken into account the command yet. CONTINUE; RX DMA Controller is transferring frames HALT; HDLC Controller2 stops the reception, generates an interrupt and waits a new command such as START or CONTINUE.
0 1 1
1 0 1
P0/1
: PROTOCOL BITS
P1 0 0 1 1 P0 0 1 0 1 HDLC Transparent Mode 1 (one byte per timeslot); the fill character defined in FCR Register is taken into account. Transparent Mode 2 (one byte per timeslot); the fill character defined in FCR Register is not taken into account. Reserved Transmission Mode
FM
: Flag Monitoring This bit is a status bit read by the microprocessor. FM=1: HDLC Controller 2 is receiving a frame or HDLC Controller 2 has just received one flag. FM is put to 0 by the microprocessor. : CRC stored in external memory CRC = 1, the CRC is stored at the end of the frame in external memory. CRC = 0, the CRC is not stored into external memory.
CRC
65/130
STLC5466
AR10
: Address Recognition10 AR10 = 1, First byte after opening flag of received frame is compared to AF0/7 bits of AFRDR. If the first byte received and AF0/7 bits are not identical the frame is ignored. AR10 = 0, First byte after opening flag of received frame is not compared to AF0/7 bits of AFRDR Register. : Address Recognition 11 AR11 = 1, First byte after opening flag of received frame is compared to all "1"s.If the first byte received is not all "1"s the frame is ignored. AR11 = 0, First byte after opening flag of received frame is not compared to all "1"s. : Address Recognition 20 AR20 = 1, Second byte after opening flag of received frame is compared to AF8/15 bits of AFRDR Register. If the second byte received and AF8/15 bits are not identical the frame is ignored. AR20 = 0, Second byte after opening flag of received frame is not compared to AF8/15 bits of AFRDR Register. : Address Recognition 21 AR21 = 1, Second byte after opening flag of received frame is compared to all "1"s. If the Second byte received is not all "1"s the frame is ignored. AR21 = 0, Second byte after opening flag of received frame is not compared to all "1"s.
AR11
AR20
AR21
Second Byte AR21 0 0 0 0 0 0 0 0 1 1 AR20 0 0 0 0 1 1 1 1 0 0
First Byte Conditions to Receive a Frame AR11 0 0 1 1 0 0 1 1 0 0 AR10 0 1 0 1 0 1 0 1 0 1 Each frame is received without condition. Only value of the first received byte must be equal to that of AF0/7 bits. Only value of the first received byte must be equal to all "1"s. The value of the first received byte must be equal either to that of AF0/7 or to all "1"s. Only value of the second received byte must be equal to that of AF8/15 bits. The value of the first received byte must be equal to that of AF0/7 bits and the value of the second received byte must be equal to that of AF8/15 bits. The value of first received byte is must be equal to all "1"s and the value of second received byte must be equal to that of AF8/15 bits. The value of the first received byte must be equal either to that of AF0/7 or to all "1"s and the value of the second received byte must be equal to that of AF8/15 bits. Only the value of the second received byte must be equal to all "1"s. The value of the first received byte must be equal to that of AF0/7 bits and the value of the second received byte must be equal to all "1"s.
66/130
STLC5466
Second Byte AR21 1 1 1 1 1 1 AR20 0 0 1 1 1 1
First Byte Conditions to Receive a Frame AR11 1 1 0 0 1 1 AR10 0 1 0 1 0 1 The value of the first received byte must be equal to all "1"s and the value of the second received byte must be equal to "1" also. The value of the first received byte must be equal either to that of AF0/7 or to "1" and the value of the second received byte must be equal to all "1"s. The value of the second received byte must be equal either to that of AF8/15 or to all "1"s. The value of the first received byte must be equal to that of AF0/7 bits and the value of the second received byte must be equal either to that of AF8/15 or to all "1"s. The value of the first received byte must be equal to "1" and the value of the second received byte must be equal either to that of AF8/15 or to all "1"s. The value of the first received byte must be equal either to that of AF0/7 or to "1" and the value of the second received byte must be equal either to that of AF8/15 or to all "1"s.
VI.39 - Address Field Recognition Address Register 2
bit15 CH4 CH3 CH2 CH1 CHO READ AMM bit8 Nu bit7 r e s e r v
AFRAR2 (5C)H
bit0 e d
After reset (0000)H
The write operation is launched when AFRAR2 is written by the microprocessor.
AMM : Access to Mask Memory AMM=1, Access to Address Field Recognition Mask Memory. AMM=0, Access to Address Field Recognition Memory. : READ ADDRESS FIELD RECOGNITION MEMORY READ=1, READ AFR MEMORY. READ=0, WRITE AFR MEMORY. : In reception these five bits define one of 32 channels of the second 32 HDLC Controller 2 named HDLC 2 connected to Din6/Dout6 of the switching matrix.
READ
CH0/4
VI.40 - Address Field Recognition Data Register 2
bit15 bit8 bit7
AFRDR2 (5E)H
bit0
AF15/ AF14/ AF13/ AF12/ AF11/ AF10/ AF9/ AF8/ AF7/ AF6/ AF5/ AF4/ AF3/ AF2/ AF1/ AF0/ AFM15 AFM14 AFM13 AFM12 AFM11 AFM10 AFM9 AFM8 AFM7 AFM6 AFM5 AFM4 AFM3 AFM2 AFM1 AFM0 After reset (0000)H AF0/15 : ADDRESS FIELD BITS if AMM=0 (AMM bit of AFRAR 2 AF0/7; First byte received; AF8/15: Second byte received. These two bytes are stored into Address Field Recognition Memory when AFRAR2 is written by the microprocessor(AMM=0). : ADDRESS FIELD BIT MASK0/15 if AMM=1 (AMM bit of AFRAR 2) AMF0/7. When AR10=1 (See HRCR2) each bit of the first received byte is compared respectively to AFx bit if AFMx=0. In case of mismatching, the received frame is ignored. If AFMx=1, no comparison between AFx and the corresponding received bit. AMF8/15. When AR20=1 (See HRCR2) each bit of the second received byte is compared respectively to AFy bit if AFMy=0. In case of mismatching, the received frame is ignored. If AFMy=1, no comparison between AFy and the corresponding received bit. These two bytes are stored into Address Field Recognition Mask Memory when AFRAR 2 is written by the microprocessor (AMM=1).
AFM0/ 15
67/130
STLC5466
VI.41 - Fill Character Register 2
bit15 r e s e r v e bit8 d bit7 FC7 FC6 FC5 FC4 FC3 FC2 FC1
FCR2 (60)H
bit0 FC0
After reset (0000)H
FC0/7
: FILL CHARACTER (eight bits) In Transparent Mode M1, two messages are separated by FILL CHARACTERS and the detection of one FILL CHARACTER marks the end of a message. SDRAMR (72)H
bit8 S R Nu Nu Nu Nu Nu bit7 Nu Nu bit5 LT1 bit4 LT0 Nu Nu Nu bit0 Nu
VI.42 - SDRAM Mode Register
bit15 T
After reset (0030)H
When the microprocessor writes in this SDRAM Mode register, the SDRAM controller initializes the SDRAM if the NINIT bit of GCR2 is at 0. When the microprocessor reads this register, the SDRAM controller is not affected. Some parameters are frozen: The option field is: Burst Read and Single Write. The Burst Length is 4. The burst data is addressed in sequential mode The programmable parameters are: LT0/1 : Latency Mode Three configurations are possible: NCAS Latency can be 1, 2 or 3)
tt
LT1 0 0 1 1
LT0 0 1 0 1
NCAS Latency Not allowed 1 2 3
The 12-bit word sent by the Multi-HDLC to initialize the SDRAM is:
bit15 Nu Nu Nu Nu Nu Nu Nu Nu bit11 0 0 0 0 1 1 bit8 0 0 bit7 0 0 LT2 0 bit5 LT1 LT1 bit4 LT0 LT0 WT 0 BL2 0 BL1 1 bit0 BL0 0
For information:
Option field: Burst Read and Single Write x x 1 0 0 Latency mode LT2 LT1 LT0 Wrap type WT Burst Length BL2 BL1 BL0
68/130
STLC5466
For information:
LT2 0 0 0 0 1 1 1 1 LT1 0 0 1 1 0 0 1 1 LT0 0 1 0 1 0 1 0 1 NCAS latency R 1 2 3 R R R R BL2 0 0 0 0 1 1 1 1 BL1 0 0 1 1 0 0 1 1 BL0 0 1 0 1 0 1 0 1 Burst Length WT=0 1 2 4 8 R R R Full page Burst Length WT=1 1 2 4 8 R R R R
T,S,R :
tt
These three bits define the SDRAM circuit organisation (1word=2bytes))
T 0 0 0 0 1 1 1 1 S 0 0 1 1 0 0 1 1 R 0 1 0 1 0 1 0 1 SDRAM circuit organization (and shared RAM organization) (1Mx16) SDRAM circuit; shared RAM up to 4M words (2Mx8) SDRAM circuit; shared RAM up to 8M words (8Mx8) SDRAM circuit; shared RAM up to 8M words (4Mx16) SDRAM circuit; shared RAM up to 8M words Reserved Reserved Reserved Reserved If refresh 2048 cycles / 32ms 4096 cycles / 64ms 4096 cycles / 64ms 4096 cycles / 64ms
VI.43 - Initiate Block Address Register 2
bit15 A23 A22 A21 A20 A19 A18 A17 bit8 A16 bit7 A15 A14 A13 A12 A11 A10
IBAR2 (74)H
bit0 A9 A8
After reset (0000)H
This register concerns the second 32 HDLC Controller 2 named HDLC 2 connected to input6/output6 of the switching matrix. The Interrupt Queue is common for the first HDLC Controller and for the second HDLC Controller 2. So this register doesn't concern the location of the Interrupt Queue.The location of the Interrupt Queue is found from the contents of the first IBAR1 register (34)H. A8/23 : Address bits. These 16 bits are the segment address bits of the Initiate Block (A8 to A23 for the external memory in the MHDLC address space).The offset is zero (A0 to A7 ="0"). The Initiate Block Address (IBA2) is:
23 A23 A22 A21 A20 A19 A18 A17 A16 A15 A14 A13 A12 A11 A10 A9 8 A8 7 0 0 0 0 0 0 0 0 0
The 23 more significant bits define one of 8 Megawords. (One word comprises two bytes.) The least significant bit defines one of two bytes when the microprocessor selects one byte. Example: MHDLC device address inside P mapping = 100000H Initiate Block for HDLC2 address inside P mapping = 310000H IBAR2 value = (310000 - 100000)/256 = 2100H
69/130
STLC5466
VI.44 - Timer Register 2
bit15 S3 S2 S1 S0 MS9 MS8 MS7 0 to 15s bit8 MS6 bit7 MS5 MS4 MS3 MS2 MS1 MS0 MM1 0 to 999ms After reset (0780)H id 480 ms
TIMR2 (7C)H
bit0 MM0 0 to 3x0.25ms
This programmable Timer Register 2 indicates the period of the Super Frame Synchronisation signal delivered by SFS pin (which is an output). The duration of the signal is 250 microseconds. The minimum programmable period is 500 microseconds. The clock frequency of the associated counter is the frequency divided by two of FS Frame Synchronisation signal applied to FS pin (which is an input).
70/130
STLC5466
VII - EXTERNAL REGISTERS These registers are located in shared memory. Initiate Block Address Registers (IBAR1 and IBAR2) give respectively the Initiate Block Address (IBA1 and IBA2) in shared memory. From IBA1 the different addresses are obtained: * Initialization Block address concerning the first HDLC Controller (HDLC1) * HDLC interrupt Queue for the first HDLC Controller (HDLC1) and the second (HDLC2) * MON interrupt Queue * C/I interrupt Queue From IBA1 only the following address is obtained: * Initialization Block address concerning the second HDLC Controller (HDLC2) `Not used' bits (Nu) are accessible by the microprocessor but the use of these bits by software is not recommended. VII.1 - Initialization Block in External Memory (IBA1 and IBA2)
Descriptor Address Channel CH 0 T Address IBA+00 IBA+02 R IBA+04 IBA+06 CH1 T IBA+08 IBA+10 R IBA+12 IBA+14 bit15 Not used bit8 bit7 TDA High bit0
Transmit Descriptor Address (TDA Low) Not used RDA High
Receive Descriptor Address (RDA Low) Not used TDA High
Transmit Descriptor Address (TDA Low) Not used RDA High
Receive Descriptor Address (RDA Low)
CH 2 to CH30
IBA+16 to IBA+246
CH 31
T
IBA+248 IBA+250
Not used
TDA High
Transmit Descriptor Address (TDA Low) Not used RDA High
R
IBA+252 IBA+254
Receive Descriptor Address (RDA Low)
When Direct Memory Access Controller receives START from one of 64 channels, it reads initialization block immediately to know the first address of the first descriptor for this channel. Bit 0 of Transmit Descriptor Address (TDA Low) and bit 0 of Receive Descriptor Address (RDA Low), are at ZERO mandatory. This Least Significant Bit is not used by DMA Controller, the shared memory is always a 16 bit memory for the DMA Controller. The Receive Descriptor Address (RDA) is never modified by the RX DMA Controller in this Initialization Block N.B. If several descriptors are used to transmit the current frame then before transmitting frame, TX DMA Controller stores the address of the first Transmit Descriptor Address (TDA) into this Initialization Block if BOF bit is at "1" (See Transmit Descriptor).
71/130
STLC5466
VII.2 - Receive Descriptor This receive descriptor is located in shared memory. The quantity of descriptors is limited by the memory size only.
15 RDA+00 RDA+02 RDA+04 RDA+06 RDA+08 RDA+10 FR ABT OVF Not used 14 SIM 13 IBC 12 EOQ Not used Receive Buffer Address Low (16 bits) NRDA High (8 bits) 11 10 9 8 7 6 5 4 3 2 1 0 0
Size Of the Buffer (SOB) RBA High (8 bits)
Next Receive Descriptor Address Low (16 bits) FCR C Number of Bytes Received (NBR)
The 5 first words located in shared memory to RDA+00 from RDA+08 are written by the microprocessor and read by the DMAC only. The 6th word located in shared memory in RDA+10 is written by the DMAC only during the frame reception and read by the microprocessor. SOB RBA RDA NBR : Size Of the Buffer associated to descriptor. These 12bits allows to reach 4096 bytes). If SOB = 0, DMAC goes to next descriptor. : Receive Buffer Address. LSB of RBA Low is at Zero mandatory. : Receive Descriptor Address. : Number of Bytes Received (up to 4096).
NRDA : Next Receive Descriptor Address. LSB of NRDA Low is at Zero mandatory.
VII.2.1 - Bits written by the Microprocessor only IBC EOQ : Interrupt if the buffer has been completed. IBC=1, the DMAC generates an interrupt if the buffer has been completed. : End Of Queue. EOQ=1, the DMAC stops immediately its reception generates an interrupt (HDLC = 1 in IR) and waits a command from the HRCR (HDLC Receive Command Register). EOQ=0, the DMAC continues. : Signal Interrupt Mask SIM=1, when an event occurs the RX DMAC thanks to Interrupt controller stores the features of this event in the HDLC Interrupt Queue but the Interrupt Register is not written. So there is no interrupt signal on INT0 pin. SIM=0, when an event occurs the RX DMAC thanks to Interrupt controller stores the features of this event in the Interrupt Queue and the HDLC bit of the Interrupt Register is put at "1". So INT0 pin goes to Vcc if HDLC bit is not masked.
SIM
VII.2.2 - Bits written by the Rx DMAC only
FR 1 1 0 0 ABT 0 0 0 0 OVF 0 0 0 0 FCRC 0 1 0 0 Definition The frame has been received without error. The end of frame is in this buffer. The frame has been received with false CRC. If NBR is different to 0, the buffer related to this descriptor is completed.The end of frame is not in this buffer. If NBR is equal to 0, the Rx DMAC is receiving a frame.
72/130
STLC5466
FR 0 0 0
ABT 1 1 1
OVF 0 1 0
FCRC 0 0 1
Definition ABORT. The received frame has been aborted by the remote transmitter or the local microprocessor. OVERFLOW of FIFO. The received frame has been aborted. The received frame had not an integer of bytes.
VII.2.3 - Receive Buffer Each receive buffer is defined by its receive descriptor. The maximum size of the buffer is 2048 words (1 word=2 bytes)
15 RBA First Buffer Location 0
RBA + SOB-2
Last Location Available = Receive Buffer Address (RBA) + Size Of the Buffer (SOB-2)
VII.3 - Transmit Descriptor This transmit descriptor is located in shared memory. The quantity of descriptors is limited by the memory size only.
15 TDA+00 TDA+02 TDA+04 TDA+06 TDA+08 TDA+10 CFT ABT UND BINT 14 BOF 13 EOF 12 EOQ 11 10 9 8 7 6 5 4 3 2 1 0
Number of Bytes to be Transmitted (NBT) CRCC PRI TBA High (8 bits)
Not used
Transmit Buffer Address Low (16 bits) Not used NTBA High (8 bits)
Next Transmit Descriptor Address Low (16 bits)
The 5 first words located in shared memory to TDA+00 from TDA+08 are written by the microprocessor and read by the DMAC only. The 6th word located in shared memory in TDA+10 is written by the DMAC only during the frame reception and read by the microprocessor. NBT TBA TDA : Number of Bytes to be transmitted (up to 4096). : Transmit Buffer Address. LSB of TBA Low is at Zero mandatory. : Transmit Descriptor Address.
NTDA : Next Transmit Descriptor Address. LSB of NTDA Low is at Zero mandatory. VII.3.1 - Bits written by the Microprocessor only BINT : Interrupt at the end of the frame or when the buffer is become empty. BINT = 1, if EOF = 1 the DMAC generates an interrupt when the frame has been transmitted; if EOF = 0 the DMAC generates an interrupt when the buffer is become empty. BINT = 0, the DMAC does not generate an interrupt during the transmission of the frame.
73/130
STLC5466
BOF : Beginning Of Frame BOF=1,the transmit buffer associated to this transmit descriptor contains the beginning of frame. The DMA Controller will store automatically the current descriptor address in the Initialization Block. BOF=0, the DMA Controller will not store the current descriptor address in the Initialization Block. : End Of Frame EOF = 1,the transmit buffer associated to this transmit descriptor contains the end of frame. EOF = 0,the transmit buffer associated to this transmit descriptor does not contain the end of frame : End Of Queue EOQ = 1, the DMAC stops immediately its transmission, generates an interrupt (HDLC = 1 in IR) and waits a command from the HTCR (HDLC Transmit Command Register). EOQ = 0, the DMAC continues.
EOF
EOQ
CRCC : CRC Corrupted CRCC = 1,at the end of this frame the CRC will be corrupted by the Tx HDLC Controller. PRI : Priority Class 8 or 10 PRI = 1, if CSMA/CR is validated for this channel, the priority class is 8. PRI = 0, if CSMA/CR is validated for this channel the priority class is 10. (see Register CSMA)
VII.3.2 - Bits written by the Tx DMAC only CFT : Frame correctly transmitted CFT = 1, the Frame has been correctly transmitted. CFT = 0, the Frame has not been correctly transmitted. : Frame Transmitting Aborted ABT = 1, the frame has been aborted by the microprocessor during the transmission. ABT = 0, the microprocessor has not aborted the frame during the transmission. : Underrun UND = 1, the transmit FIFO has not been fed correctly during the transmission. UND = 0, the transmit FIFO has been fed correctly during the transmission.
ABT
UND
VII.3.3 - Transmit Buffer Each transmit buffer is defined by its transmit descriptor. The maximum size of the buffer is 2048 words (1 word=2 bytes)
15 TBA First Word to Transmit 0
TBA + x; NBT is odd: x = NBT - 1 NBT is even: x = NBT - 2
Last Word to Transmit
74/130
STLC5466
VII.4 - Receive & Transmit HDLC Frame Interrupt
bit15 NS A5 Tx A4 A3 A2 A1 A0 bit8 0 bit7 0 0 CFT/CFR BE/BF HALT EOQ bit 0 RRLF/ERF
This word is located in the HDLC interrupt queue; IQSR Register indicates the size of this HDLC interrupt queue located in the external memory. NS : New Status. Before writing the features of event in the external memory the Interrupt Controller reads the NS bit: if NS = 0, the Interrupt Controller puts this bit at `1' when it writes the status word of the frame which has been transmitted or received. if NS = 1, the Interrupt Controller puts ICOV bit at `1' to generate an interrupt (IR Register). When the microprocessor has read the status word, it puts this bit at `0' to acknowledge the new status. This location becomes free for the Interrupt Controller. : 32 HDLC controller A5 = 1, Second 32 HDLC controller (connected to Dout6/ Din6 of the switching matrix). A5 = 0, First 32 HDLC controller (connected to Dout7/ Din7 of the switching matrix).
A5
Transmitter Tx A4/0 : Tx = 1, Transmitter : Tx HDLC Channel 0 to 31
RRLF : Ready to Repeat Last Frame In consequence of event such as Abort Command HDLC, Controller is waiting Start or Continue EOQ : End of Queue The Transmit DMA Controller has encountered the current Transmit Descriptor with EOQ at "1". DMA Controller is waiting "Continue" from microprocessor.
HALT : The Transmit DMA Controller has received HALT from the microprocessor; it is waiting "Continue" from microprocessor. BE : Buffer empty If BINT bit of Transmit Descriptor is at `1', the Transmit DMA Controller puts BE at "1" when the buffer has been emptied. : Correctly Frame Transmitted A frame has been transmitted. This status is provided only if BINT bit of Transmit Descriptor is at `1'. CFT is located in the last descriptor if several descriptors are used to define a frame.
CFT
Receiver Tx A4/0 ERF EOQ : Tx = 0, Receiver : Rx HDLC Channel 0 to 31 : Error detected on Received Frame An error such as CRC not correct, Abort, Overflow has been detected. : End of Queue The Receive DMA Controller has encountered the current receive Descriptor with EOQ at "1". DMA Controller is waiting "Continue" from microprocessor.
HALT : The Receive DMA Controller has received HALT or ABORT (on the outside of frame) from the microprocessor; it is waiting "Continue" or "Start" from the microprocessor. BF : Buffer Filled If IBC bit of Receiver Descriptor is at `1', the Receive DMA Controller puts BF at"1" when it has filled the current buffer with data from the received frame.
75/130
STLC5466
CFR : Correctly Frame Received CFR =1, a receive frame is ended with a correct CRC. The end of the frame is located in the last descriptor if several Descriptors.
VII.5 - Receive Command / Indicate Interrupt VII.5.1 - Receive Command / Indicate Interrupt when TSV = 0 Time Stamping not validated (bit of GCR Register)
bit15 NS NS Nu Nu S1 S1 S0=0 S0=1 G0 G0 A2 A2 A1 A1 bit8 A0 A0 bit7 Nu Nu Nu Nu C6 A C5 E C4 S1 C3 S2 C2 S3 bit 0 C1 S4
This word is located in the Command/Indicate interrupt queue; IQSR Register indicates the size of this interrupt queue located in the external memory. NS : New Status. Before writing the features of event in the external memory the Interrupt Controller reads the NS bit: if NS = 0, the Interrupt Controller puts this bit at `1' when it writes the new primitive which has been received. if NS = 1, the Interrupt Controller puts ICOV bit at `1' to generate an interrupt (IR Register). When the microprocessor has read the status word, it puts this bit at `0' to acknowledge the new status. This location becomes free for the Interrupt Controller. : G0 = 0, GCI 0 corresponding to DIN4 input and DOUT4 output. G0 = 1, GCI 1 corresponding to DIN5 input and DOUT5 output. : COMMAND/INDICATE Channel 0 to 7 being owned by GCI 0 or GCI 1 : Primitive or 6 bit word or AIS received : New Primitive received twice consecutively. Case of S0=S1=0 6 bits received twice consecutively. Case of S0=1 S1=0.
G0 A2/0 S1/0 C6/1 A, E, S1/S4
S1 0 0 0 0 1 1 1
S0 0 0 1 1 0 0 1
G0 0 1 0 1 0 1 0
Word stored in shared memory Primitive C1/6 received from GCI Multiplex 0 corresponding to DIN4 Primitive C1/6 received from GCI Multiplex 1 corresponding to DIN5 A, E, S1/S4 bits from any input timeslot switched to one timeslot 4n+3 of GCI Multiplex 0 without outgoing to DOUT4 A, E, S1/S4 bits from any input timeslot switched to one timeslot 4n+3 of GCI 1 without outgoing to DOUT5 AIS detected during more 30 ms from any input timeslot and switched to B1, B2 channels (16 bits) of the GCI Multiplex 0 (DOUT4) in transparent mode or not AIS detected during more 30 ms from any input timeslot and switched to B1, B2 channels (16 bits) of the GCI Multiplex 1 (DOUT5) in transparent mode or not. Reserved
76/130
STLC5466
VII.5.2 - Receive Command / Indicate Interrupt when TSV = 1 Time Stamping validated (bit of GCR Register)
bit15 NS T15 Nu T14 Nu T13 Nu T12 G0 T11 A2 T10 A1 T9 bit8 A0 T8 bit7 Nu T7 Nu T6 C6 T5 C5 T4 C4 T3 C3 T2 C2 T1 bit 0 C1 T0
These two words are located in the Command/Indicate interrupt queue; IQSR Register indicates the size of this interrupt queue located in the external memory. NS : New Status. Before writing the features of event in the external memory the Interrupt Controller reads the NS bit: if NS = 0, the Interrupt Controller puts this bit at `1' when it writes the new primitive which has been received. if NS = 1, the Interrupt Controller puts ICOV bit at `1' to generate an interrupt (IR Register). When the microprocessor has read the status word, it puts this bit at `0' to acknowledge the new status. This location becomes free for the Interrupt Controller. : G0 = 0, GCI 0 corresponding to DIN4 input and DOUT4 output. G0 = 1, GCI 1 corresponding to DIN5 input and DOUT5 output. : COMMAND/INDICATE Channel 0 to 7 being owned by GCI 0 or GCI 1 : New Primitive received twice consecutively
G0 A2/0 C6/1
T15/0 : Binary counter value when a new primitive is occurred. VII.6 - Receive Monitor Interrupt VII.6.1 - Receive Monitor Interrupt when TSV = 0 TSV: Time Stamping not Validated (bit of GCR Register)
bit15 NS M18 M17 M16 M15 G0 M14 A2 M13 A1 M12 bit8 A0 M11 M8 M7 M6 M5 bit7 ODD M4 A M3 F M2 bit 0 L M1
These two words are transferred into the Monitor interrupt queue; IQSR Register indicates the size of this interrupt queue located in the external memory. NS : New Status. Before writing the features of event in the external memory the Interrupt Controller reads the NS bit: if NS = 0, the Interrupt Controller stores two new bytes M1/8 and M11/18 then puts NS bit at `1' when it writes the status of these two bytes which has been received. if NS = 1, the Interrupt Controller puts ICOV bit at `1' to generate an interrupt (IR Register). : G0 = 0, GCI 0 corresponding to DIN4 input and DOUT4 output. G0 = 1, GCI 1 corresponding to DIN5 input and DOUT5 output. : Last byte L=1, two cases: if ODD = 1, the following word of the Interrupt Queue contains the Last byte of message. if ODD =0, the Last byte of message has been stored at the previous access of the Interrupt Queue (concerning this channel). L=0, the following word and the previous word does not contain the Last byte of message. : First byte F=1, the following word contains the First byte of message. F=0, the following word does not contain the First byte of message.
G0 L
F
77/130
STLC5466
A : Abort A=1, Received message has been aborted.
ODD : Odd byte number ODD = 1, one byte has been written in the following word. ODD = 0, two bytes have been written in the following word. In case of V* protocol ODD,A,F,L bits are respectively 1,0,1,1. M1/8 : New Byte received twice consecutively if GCI Protocol has been validated. Byte received once if V* Protocol has been validated.
M11/18 : Next new Byte received twice consecutively if GCI Protocol has been validated. This byte is at "1" in case of V* protocol. VII.6.2 - Receive Monitor Interrupt when TSV = 1 TSV: Time Stamping Validated (bit of GCR Register)
bit15 NS M18 T15 0 M17 T14 0 M16 T13 0 M15 T12 0 G0 M14 T11 0 A2 M13 T10 0 A1 M12 T9 0 bit8 A0 M11 T8 0 M8 T7 0 M7 T6 0 M6 T5 0 M5 T4 0 bit7 ODD M4 T3 0 A M3 T2 0 F M2 T1 0 bit 0 L M1 T0 0
These four words are located in the Monitor interrupt queue; IQSR Register indicates the size of this interrupt queue located in the external memory. NS : New Status. Before writing the features of event in the external memory the Interrupt Controller reads the NS bit: if NS = 0, the Interrupt Controller stores two new bytes M1/8 and M11/18 then puts NS bit at `1' when it writes the status of these two bytes which has been received. if NS = 1, the Interrupt Controller puts ICOV bit at `1' to generate an interrupt (IR Register). : G0 = 0, GCI 0 corresponding to DIN4 input and DOUT4 output. G0 = 1, GCI 1 corresponding to DIN5 input and DOUT5 output. : Last byte L=1, two cases: if ODD = 1, the following word of the Interrupt Queue contains the Last byte of message. if ODD =0, the Last byte of message has been stored at the previous access of the Interrupt Queue (concerning this channel). L=0, the following word and the previous word does not contain the Last byte of message. : First byte F=1, the following word contains the First byte of message. F=0, the First byte of message is not the following word. : Abort A=1, Received message has been aborted. Odd byte number ODD = 1, one byte has been written in the following word. ODD = 0, two bytes have been written in the following word. : New Byte received twice consecutively if GCI Protocol has been validated. Byte received once if V* Protocol has been validated.
G0 L
F
A ODD
M1/8
M11/18 : Next new Byte received twice consecutively if GCI Protocol has been validated. This byte is at "1" in case of V* protocol. T15/0
78/130
: Binary counter value when a new primitive is occurred.
STLC5466
VIII - TQFP176 PACKAGE MECHANICAL DATA
DIM. MIN. A A1 A2 B C D D1 D3 e E E1 E3 L L1 K 0.45 0.05 1.35 0.17 0.09 26.00 24.00 21.50 0.50 26.00 24.00 21.50 0.60 1.00 0.75 0.018 1.40 0.22 mm TYP. MAX. 1.60 0.15 1.45 0.27 0.20 0.002 0.053 0.007 0.003 1.024 0.945 0.846 0.019 1.024 0.945 0.846 0.024 0.0393 3.5(min.), 7(max.) 0.030 0.055 0.009 MIN. inch TYP. MAX. 0.063 0.006 0.057 0.011 0.008
OUTLINE AND MECHANICAL DATA
TQFP176 (24x24x1.40mm)
D D1 A D3 A1 132 133 89 88
0.076mm .003 inch Seating Plane
A2
B
B
E3
PIN 1 IDENTIFICATION
E1
E
176 1 e 44
45 C
L1 L
K
TQFP176M
79/130
STLC5466
IX - FIGURES and TIMING SEE FOLLOWING DOCUMENT These FIGURES must be located in the following paragraphs: Figure 1-1: MHDLC Block diagram in paragraph II Figure 1-2: Variable delay through the matrix with ITDM=1 in paragraph III 5.1 Figure 1-3: Variable delay through the matrix with ITDM=0 in paragraph III 5.1 Figure 1-4: Constant delay through the matrix with SI=1 in paragraph III 5.1 Figure 1-5: Downstream switching at 32 kb/s in paragraph III 1.7 Figure 1-6: Upstream switching at 32 kb/s in paragraph III 1.7 Figure 1-7: Upstream and downstream switching at 16 Kbit/s in paragraph III 1.8 Figure 1-8: D,C/I and Monitor channel path in paragraph III 3.3 Figure 1-9: GCI channel to/from ISDN channel in paragraph III 5 Figure 1-10: From GCI channels to ISDN channels in paragraph III 5 Figure 1-11: From ISDN channels to GCI channels in paragraph III 5 Figure 1-12: Multi-HDLC connected to mP with multiplexed buses in paragraph III 6.2.3 Figure 1-13: Multi-HDLC connected to mP with non multiplexed buses in paragraph III 6.2.3 Figure 1-14: Microprocessor interface for INTEL 80C188 in paragraph III 6.2.3 Figure 1-15: Microprocessor interface for INTEL 80C186 in paragraph III 6.2.3 Figure 1-16: Microprocessor interface for MOROLA 68000 in paragraph III 6.2.3 Figure 1-17: Microprocessor interface for MOROLA 68020 in paragraph III 6.2.3 Figure 1-18: Microprocessor interface for ST9 in paragraph III 6.2.3 Figure 1-19: Microprocessor interface for INTEL 386EX in paragraph III 6.2.3 Figure 1-20: Ex1; different clocks for Multi-HDLC and mP in paragraph III 6.2.3 Figure 1-21: Ex2; synchronous clock for Multi-HDLC and mP in paragraph III 6.2.3 Figure 1-22: 4Mx16 SDRAM memory organisation in paragraph III 7.4.1 Figure 1-23: First example, 8Mx16 SDRAM memory organisation in paragraph III 7.4.2 Figure 1-24: Second example, 8Mx16 SDRAM memory organisation in paragraph III 7.4.3 Figure 1-25: Third example, 8Mx16 SDRAM memory organisation in paragraph III 7.4.4 Figure 1-26: Chain of n Multi-HDLC components in paragraph III 8 Figure 1-27: MHDLC clock generation in paragraph III 9.1 Figure 1-28: VCXO frequency synchronization in paragraph III 9.2 Figure 1-29: The three circular interrupt memories in paragraph III 10.5
80/130
STLC5466
LIST OF FIGURES
1
FIGURES associated with text . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 Figure 1-1: MHDLC Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 Figure 1-2: Variable delay through the matrix with ITDM=1 . . . . . . . . . . . . . . . . . . . . 84 Figure 1-3: Variable delay through the matrix with ITDM=0 . . . . . . . . . . . . . . . . . . . . 85 Figure 1-4: Constant delay through the matrix with SI=1. . . . . . . . . . . . . . . . . . . . . . . 86 Figure 1-5: Downstream switching at 32 kb/s . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 Figure 1-6: Upstream switching at 32 kb/s . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 Figure 1-7: Upstream and downstream switching at 16 Kbit/s . . . . . . . . . . . . . . . . . . 89 Figure 1-8: D, C/I and Monitor channel path . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 Figure 1-9: GCI channel to/from ISDN channel . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 Figure 1-10: From GCI channels to ISDN channels . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 Figure 1-11: From ISDN channels to GCI channels . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 Multi-HDLC connected to mP with multiplexed buses. . . . . . . . . . . . . . . . 94 Figure 1-12: Multi-HDLC connected to mP with non multiplexed buses . . . . . . . . . . . . 94 Figure 1-13: Figure 1-14: Microprocessor interface for INTEL 80C188 . . . . . . . . . . . . . . . . . . . . . . . 95 Figure 1-15: Microprocessor interface for INTEL 80C186 . . . . . . . . . . . . . . . . . . . . . . . 95 Figure 1-16: Microprocessor interface for MOROLA 68000 . . . . . . . . . . . . . . . . . . . . . 96 Figure 1-17: Microprocessor interface for MOROLA 68020 . . . . . . . . . . . . . . . . . . . . . 96 Figure 1-18: Microprocessor interface for ST9 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 Figure 1-19: Microprocessor interface for INTEL 386EX. . . . . . . . . . . . . . . . . . . . . . . . 97 Figure 1-20: Ex1; different clocks for Multi-HDLC and mP . . . . . . . . . . . . . . . . . . . . . . 98 Figure 1-21: Ex2; synchronous clock for Multi-HDLC and mP . . . . . . . . . . . . . . . . . . . 98 Figure 1-22: 4Mx16 SDRAM memory organisation . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 Figure 1-23: First example, 8Mx16 SDRAM memory organisation . . . . . . . . . . . . . . . 100 Figure 1-24: Second example, 8Mx16 SDRAM memory organisation . . . . . . . . . . . . 101 Figure 1-25: Third example, 8Mx16 SDRAM memory organisation . . . . . . . . . . . . . . 102 Figure 1-26: Chain of n Multi-HDLC components . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 Figure 1-27: MHDLC clock generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 Figure 1-28: VCXO frequency synchronization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 Figure 1-29: The three circular interrupt memories . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 CLOCK and TDMs TIMING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Figure 2-1: Clocks received and delivered by the Multi-HDLC . . . . . . . . . . . . . . . . . Figure 2-2: Synchronization signals received by the Multi-HDLC . . . . . . . . . . . . . . . Figure 2-3: GCI Synchro signal delivered by the Multi-HDLC . . . . . . . . . . . . . . . . . . Figure 2-4: V* Synchronisation signal delivered by the Multi-HDLC . . . . . . . . . . . . . 106 106 107 108 109
2
3
SDRAM MEMORY TIMING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110 Figure 3-1: Signals exchanged between SDRAM controller and SDRAM. . . . . . . . . 110 MICROPROCESSOR TIMING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Figure 4-1: ST 9 read cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Figure 4-2: ST 9 write cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Figure 4-3: ST10 (C16x) read cycle; multiplexed A/D . . . . . . . . . . . . . . . . . . . . . . . . Figure 4-4: ST10 (C16x) write cycle; multiplexed A/D . . . . . . . . . . . . . . . . . . . . . . . . 111 111 112 113 114
4
81/130
STLC5466
Figure 4-5: Figure 4-6: Figure 4-7: Figure 4-8: Figure 4-9: Figure 4-10: Figure 4-11: Figure 4-12: Figure 4-13: Figure 4-14: Figure 4-15: Figure 4-16: Figure 4-17: 5 ST10 (C16x) read cycle; demultiplexed A/D . . . . . . . . . . . . . . . . . . . . . . ST10 (C16x) write cycle; demultiplexed A/D . . . . . . . . . . . . . . . . . . . . . . 80C188 read cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80C188 write cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80C186 read cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80C186 write cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 386EX read cycle (LBA# at Vdd). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 386EX write cycle (LBA# at Vdd) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 386EX; NRDY versus LBA# . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68000 read cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68000 write cycle. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68020 read cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68020 write cycle. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 116 117 118 119 120 121 122 123 124 125 126 127
MASTERCLOCK and TOKEN RING TIMING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 Figure 5-1: Masterclock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 Figure 5-2: Token ring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129
82/130
STLC5466
1 FIGURES associated with text
Figure 1-1: MHDLC Block diagramL NDIS DOUT 0 DOUT 1 DOUT 2 DOUT 3 DOUT 4 DOUT 5 DOUT 6 DOUT 7
V10b V10a
DIN 7 DIN 6
DIN 5 DIN 4 DIN 3 DIN 2 DIN 1 DIN 0
GCI1 GCI0
0 1 2 3 4 5 6
D6
SWITCHING MATRIX 0 n x 64 kb/s 1 Scrambler/Descrambler 2 for 32 channels
GCI0 GCI1
7
RX GCI
D7
Pseudo Random Sequence Analyser
Pseudo Random Sequence Generator
3 4 5 6 7
TX GCI
DIN 9 CB1
V10a
V10b
DIN 8 FIRST TIME SLOT ASSIGNER EC1 CB2
V10a
SECOND TIME SLOT ASSIGNER EC2
V10b
FIRST SECOND 32 RX HDLC 32 RX HDLC with Address with Address Recognition Recognition 32 RX DMAC 32 RX DMAC Internal Bus Microprocessor interface
SECOND 32 TX HDLC with CSMA CR for Contention Bus 32 TX DMAC
FIRST 32 TX HDLC with CSMA CR for Contention Bus 32 TX DMAC SDRAM Controller V10a, bit V10 of TADR1 V10b, bit V10 of TADR2 D6, bit of GCR2 D7, bit of GCR1
BUS ARBITRATION
83/130
STLC5466
Figure 1-2: Variable delay through the matrix with ITDM=1
1)case: If OTSy > ITSx + 2, then Variable Delay is: Frame n Input Frame
ITS0 ITSx ITSx+1 ITSx+2 ITS31 ITS0
OTSy - ITSx Time slots Frame n + 1
ITS31
y > x+ 2
Output Frame
OTS0
OTS31 OTSy
Variable Delay (OTSy -ITSx)
2)case: If ITSx OTSy ITSx+2, then Variable Delay is: Input Frame
ITS0 ITSx ITSx+1 ITSx+2 ITS31 ITS0
OTSy-ITSx+32 Time slots
ITSx ITS31
x y x+2
Output Frame
OTS0 OTSy
OTS31
32 Timeslots Variable Delay:
OTSy
OTSy - ITSx + 32 Timeslots
3)case: If Input Frame
OTSy < ITSx, then Variable Delay is:
ITS0 ITSx ITS31
32 - (ITSx - OTSy) Time slots
ITS0 ITSx ITS31
yOutput Frame
OTS0 OTSy
OTS31
Variable Delay: 32 - (ITSx - OTSy) Timeslots 32 Timeslots
OTSy
84/130
STLC5466
Figure 1-3: Variable delay through the matrix with ITDM=0
1)case: If OTSy > ITSx + 1, then Variable Delay is: Frame n Input Frame
ITS0 ITSx ITSx+1 ITSx+2 ITS31 ITS0
OTSy - ITSx Time slots Frame n + 1
ITS31
y > x+ 1
Output Frame
OTS0
OTS31
Variable Delay (OTSy -ITSx)
OTSy
2)case: If Input Frame
ITSx OTSy ITSx+2, then Variable Delay is:
ITS0 ITSx ITSx+1 ITSx+2 ITS31 ITS0
OTSy-ITSx+32 Time slots
ITSx ITS31
x y x+1
Output Frame
OTS0 OTSy
OTS31
32 Timeslots Variable Delay:
OTSy
OTSy - ITSx + 32 Timeslots
3)case: If Input Frame
OTSy < ITSx, then Variable Delay is:
ITS0 ITSx ITS31
32 - (ITSx - OTSy) Time slots
ITS0 ITSx ITS31
yOutput Frame
OTS0 OTSy
OTS31
Variable Delay: 32 - (ITSx - OTSy) Timeslots 32 Timeslots
OTSy
85/130
STLC5466
Figure 1-4: Constant delay through the matrix with SI=1
Constant Delay = (32 - ITSx) + 32 + OTSy
ITS: Input Timeslot 0 x 31 0 y 31 OTS: Output Timeslot
Frame n
ITS0
Frame n+1
ITS31 ITS0 ITS31 ITS0
Frame n+2
ITS31
Min Constant Delay = 33TS OTS0 1 + 32 Timeslots +0 OTS31 =33 Timeslots
Max Constant Delay = 95Timeslots OTS31 32 - 0 + 32 + 31 = 95 Timeslots
(32 -ITSx)
+ 32
+ OTSy
= Constant Delay
86/130
STLC5466
Figure 1-5: Downstream switching at 32 kb/s
3.9ms
DIN0
a
b
Free
c
Free
d
Free
e
din2
a
b
c
d
e
dout2
c
a
dout4 Internal command If SW0=1 DOUT4 (GCI 0)
d
b
MON
D C/I
d
c
b
a
D
C/I
AE
B1
B2
MON
D
C/I AE
DOUT 4 (GCI 0) DOUT2
dout 4 dout 2 Internal commands
din 0 4 bit shifting din 2
SW0=1
DIN0
DIN2 not used Switching at 32 kb/s
DOUT 5 (GCI 1) DOUT3
dout 5 dout 3
din 1 4 bit shifting din 3
SW1=1
DIN 1
DIN3 not used
MULTI HDLC STLC 5466
87/130
STLC5466
Figure 1-6: Upstream switching at 32 kb/s
Timeslot (3.9ms) DIN4 (GCI 0) d B1 DOUT6 B2 GCI 1 DIN6 = shifted DOUT6 B2 GCI1 a DOUT0 Free b d c b c b B2 a x a MON y D C/I z B2 GCI 1 y
B1 GCI 0 d c
B2 GCI 0 b a
B1 GCI 1 x
B1 GCI 0 Free c
B2 GCI 0 Free d
B1 GCI 1 Free e
DOUT 0 Internal loopback and 4 bit shifting (2+2) by software
DIN4
GCI 0
From DOUT6
DOUT6 Switching at 32 kb/s DOUT1
DIN6
DIN 5
GCI1
MULTI HDLC STLC 5466
88/130
STLC5466
Figure 1-7: Upstream and downstream switching at 16 Kbit/s
TDM side
D11 D12 D21 TSy D22 D31 D32 D41 D42
GCI side
D11 D12 C1 C2 C3 C4 A E
TS 16n+3
D21
TSy of any TDM can be programmable with y comprised between 0 and 31.
D22 C1 C2 C3 C4 A E
TS 16n+7
D31 D32 C1 C2 C3 C4 A E
TS 16n+11
D41 D42 C1 C2 C3 C4 A E
TS 16n+15
n: GCI channel number, 0 to 1
89/130
STLC5466
Figure 1-8: D, C/I and Monitor channel path
DIN 5
GCI1 GCI0
DIN 4
DOUT 4
from TX HDLC2
0 1 2 3 4 5 6 7
SWITCHING MATRIX
0 1 2 3 4 5 6 7
GCI0
GCI1
DOUT 5
to RX HDLC 2
from TX HDLC1 16D Channels
to RX HDLC1 16D Channels
GCI CHANNEL DEFINITION
16 RX C/I
16 RX MON
16 TX C/I
16 TX MON
Interrupt Controller
From/ to
Internal Bus
From/to SDRAM
90/130
STLC5466
Figure 1-9: GCI channel to/from ISDN channel
TDM side
B1 B1 B1 B1
GCI side
B1 B1 B1 B1 B1 B1 B1 B1 B1 B2 B2 B2 B2 B2 B2 B2 B2 M1 M2 M3 M4 M5 M6 M7 M8 D D C1 C2 C3 C4 A E
TS3m
B1 B1 B1 B1 B1 B2 B2 B2 B2 B2 B2 B2 B2 D D A E S1 S2 S3 S4
SCRAMBLER / DESCRAMBLER
TS4n
TS3m+1
SCRAMBLER / DESCRAMBLER
TS4n+1
TS3m+2
TS4n+2
PCM at 2 Mb/s m: ISDN channel number, 0 to 9 If TDM at 4 Mb/s odd timeslot or even timeslot can be selected
TS4n+3
n: GCI channel number, 0 to 7
Six bit word RX
Primitive Monitor controllers TX RX TX
Command Indicate controllers
C/I interrupt Queue located in shared memory
Microprocessor
MON interrupt Queue located in shared memory
91/130
STLC5466
Figure 1-10: From GCI channels to ISDN channels
SCRAMBLER up to 32 SCR by timeslot
SBV for the 16 controllers
Extension TX C/I controllers up to 16 for A, E, S1 to S4
TDM 0, 2 if PCM at 4 Mb/s
1 B1, B2 D, A, E S1 to S4 SWITCHING MATRIX
GCI side DIN4/5
RX C/I controllers up to 16 for primitives
RX MON controllers up to 16
Interrupt controller
Microprocessor
C/I interrupt Queue, MON interrupt Queue, located in shared memory
92/130
STLC5466
Figure 1-11: From ISDN channels to GCI channels
DESCRAMBLER up to 32 SCR by timeslot
TDM 0, 2 if PCM at 4 Mb/s
SWITCHING MATRIX
B1, B2 B1, B2 D
GCI side DOUT4/5
B1, B2 (16 bits)
A, E, S1 to S4
C/I
A, E, MON
AIS Detection up to 16 ISDN channels
Extension RX C/I controller up to 16 ISDN channels
TX C/I controller up to 16 primitives
TX MON controller up to 16 primitives
Interrupt controller
C/I interrupt Queue, located in shared memory
Microprocessor
93/130
STLC5466
Figure 1-12: Multi-HDLC connected to P with multiplexed buses
MULTI-HDLC
mP ST9/10 Intel Motorola 8/16 bits
multiplex address/data bus address bus
mP INTER FACE
internal bus
SDRAM INTER FACE
data bus
Synchronous Dynamic RAM (organised by 16 bits)
BUS ARBITRATION
Figure 1-13: Multi-HDLC connected to P with non multiplexed buses
MULTI-HDLC
mP address bus ST10 Intel data bus Motorola 8/16/32 bits
address bus
mP INTER FACE
internal bus
RAM INTER FACE
data bus
Synchronous Dynamic RAM (organised by 16 bits)
BUS ARBITRATION
94/130
STLC5466
Figure 1-14: Microprocessor interface for INTEL 80C188
INT0/1
WDO
NRESET CS0/1
INTEL 80C188
ARDY NWR NRD ALE A8/19 AD0/7
mP INTERFACE
Figure 1-15: Microprocessor interface for INTEL 80C186
INT0/1
WDO
NRESET CS0/1 NBHE
INTEL 80C186
ARDY NWR NRD ALE A16/19 AD0/15
mP INTERFACE
95/130
STLC5466
Figure 1-16: Microprocessor interface for MOROLA 68000
INT0/1
WDO
NRESET CS0/1 NDTACK
MOTOROLA 68000
R/NW NUDS NLDS NAS A1/23 AD0/15
mP INTERFACE
Figure 1-17: Microprocessor interface for MOROLA 68020
INT0/1
WDO
NRESET CS0/1 NDSACK0/1
MOTOROLA 68020
SIZE0/1 R/NW NDS NAS A0/23 AD0/15
mP INTERFACE
96/130
STLC5466
Figure 1-18: Microprocessor interface for ST9
INT0/1
WDO
NRESET CS0/1
ST9
WAIT R/NW NDS NAS A8/15 AD0/7
mP INTERFACE
Figure 1-19: Microprocessor interface for INTEL 386EX
INT0/1
WDO NRESET CLKOUT NCS0/2
386EXTB
NADS NBHE, NBLE NLBA WNRD NRDY A1/23 D0/15
mP INTERFACE STLC5466
97/130
STLC5466
1.1 Microprocessor, MHDLC, SDRAM clock distribution
Figure 1-20: Ex1; different clocks for Multi-HDLC and P
External clock generation for mP
External clock generation for Multi-HDLC and SDRAM MCLK
CLK
Multi-HDLC mP STLC5466
Shared memory SDRAM
mP bus MCLK: Master Clock of the Multi-HDLC and CLK Clock of the SDRAM are the same mandatory. SDRAM bus
Figure 1-21: Ex2; synchronous clock for Multi-HDLC and P
External clock generation 50 MHz
MCLK Internally 50/2 = 25MHz mP 386EXTB
CLK
Multi-HDLC STLC5466
Shared memory SDRAM
mP bus MCLK, Master Clock of the Multi-HDLC, Master Clock of the mP and CLK Clock of the SDRAM are the same. SDRAM bus
98/130
STLC5466
1.2 Memory obtained with 1M x16 SDRAM circuit
Signals NCE3 NCE2 NCE1 NCE0
A22 1 1 0 0
A21 1 0 1 0
Signals
A0 (or equivalent)
UDQM LDQM
1 0
The Address bits delivered by the Multi-HDLC for 1M x n SDRAM circuits are: ADM11 for Bank select corresponding with A20 delivered by the P ADM0/10 for Row address inputs corresponding with A9/19 delivered by the P ADM0/7 for Column address inputs corresponding with A1/8 delivered by the P Figure 1-22: 4Mx16 SDRAM memory organisation
UDQM
LDQM
ADM0/11, NWE, NRAS, NCAS, MCLK are connected to each circuit 6
NCE3
7
NCE2
5
4
NCE1
3
2
NCE0
1
0
1M x 16 circuit two banks 512 Kwords (16 bits) by bank
DM8/15
DM0/7
99/130
STLC5466
1.3 Memory obtained with 2M x 8 SDRAM circuit
Signals NCE3 NCE2 NCE1 NCE0
A23 1 1 0 0
A22 1 0 1 0
Signals
A0
NLDS
NUDS
UDQM LDQM
1 0
0 1
1 0
The Address bits delivered by the Multi-HDLC for 2M x n SDRAM circuits are: ADM11 for Bank select corresponding with A21 delivered by the P ADM0/10 for Row address inputs corresponding with A10/20 delivered by the P ADM0/8 for Column address inputs corresponding with A1/9delivered by the P Figure 1-23: First example, 8Mx16 SDRAM memory organisation
UDQM
LDQM
ADM0/11, NWE, NRAS, NCAS, MCLK are connected to each circuit 6
NCE3
7
NCE2
5
4
NCE1
3
2 2M x 8 circuit: two banks 1Mbyte by bank
NCE0
1
0 2M x16 with 2 circuits DM8/15 DM0/7
100/130
STLC5466
1.3.0.1 Memory obtained with 8M x 8 SDRAM circuit:
Signals UDQM LDQM
A0 1 0
NLDS 0 1
NUDS 1 0
The Address bits delivered by the Multi-HDLC for 8M x n SDRAM circuits are: ADM12/13 for Bank select corresponding with A22/23 delivered by the P ADM0/11 for Row address inputs corresponding with A10/21 delivered by the P ADM0/8 for Column address inputs corresponding with A1/9 delivered by the P Figure 1-24: Second example, 8Mx16 SDRAM memory organisation
ADM0/13, NCE, NWE, NRAS, NCAS, MCLK are connected to each circuit
UDQM
LDQM
8M x 16 with 2 circuits
NCE
1
0
8M x 8 circuit: four banks 2Mbytes by bank DM0/7
DM8/15
101/130
STLC5466
1.3.0.2 Memory obtained with 4M x 16 SDRAM circuit:
Signals NCE1 NCE0
A23
Signals UDQM LDQM
A0 1 0
NLDS 0 1
NUDS 1 0
1 0
The Address bits delivered by the Multi-HDLC for 4M x n SDRAM circuits are: ADM12/13 for Bank select corresponding with A21/22 delivered by the P ADM0/11 for Row address inputs corresponding with A9/20 delivered by the P ADM0/7 for Column address inputs corresponding with A1/8 delivered by the P Figure 1-25: Third example, 8Mx16 SDRAM memory organisation
UDQM
LDQM
ADM0/13, NWE, NRAS, NCAS, MCLK are connected to each circuit
NCE1
6
7
NCE0
5
4
4M x16 circuit DM8/15 DM0/7
102/130
STLC5466
Figure 1-26: Chain of n Multi-HDLC components
TRI mP MHDLC 0 TRO RAM
TRI MHDLC 1 TRO
TRI MHDLC n mP bus TRO SDRAM bus
103/130
STLC5466
Figure 1-27: MHDLC clock generation
Ref. Clock RESET
FRAME A CLOCK A
INT1
FSCV*
Clock Lack Detection from 250 ms
Frame CLOCK SELECTION
FRAME B CLOCK B
CLOCK
FSCGCI
Clock ADAPTATION
DCLK
At RESET FRAME A and CLOCK A are selected Clock Supervision Deactivation (CSD) A or B Selected (BSEL) HCL
Select A or B (SELB)
SYN1 SYN0 To the internal MHDLC
General Configuration Register (GCR)
104/130
STLC5466
Figure 1-28: VCXO frequency synchronization
VCXO f=15360 kHz or 16384 kHz f/p VCXO-IN OUX Ref/8
Low Pass Filter
VCXO-OUT
If f=15360 kHz, p=30 If f=16384 kHz, p=32
Ref=4096 kHz
MHDLC
EVM
Figure 1-29: The three circular interrupt memories
IBA1
IBA1+256
IBA1+256 +HDLC Queue Size
Initialization Block 1
HDLC Interrupt Queue for 64 TXchannels and 64 RX channels
MON Interrupt Queue for 16 RX MON channels
IBA1+256 +HDLC Queue Size +MON Queue Size
C/I Interrupt Queue for 16 RX C/I channels
IBA1+254
105/130
STLC5466
2 CLOCK and TDMs TIMING
2.1 Synchronization signals delivered by the system For one of three different input synchronizations which is programmed, FSCG and FSCV* signals delivered by the Multi-HDLC are in accordance with the figure hereafter: Figure 2-1: Clocks received and delivered by the Multi-HDLC
CLOCK B
t2
CLOCK A 3 4
t5h t5l
t1
5
6
7
0
1
1) Sy Mode
FRAME A or B
t3 t4 2) GCI Mode
FRAME (A or B)
t3 t4
t3
t4 GCI
3) V* Mode
FRAME A (or B) DIN 0/8, Echo D0UT 0/7, CB If FS=FSCG TDMO/7 Time Slot 23 (if 1536 kbit/s) FSCG delivered by the circuit FSC V* delivered by the circuit
Bit3
Bit4
Bit5
Bit6
Bit7
Bit0
Bit1
Time Slot 31 (if 2048 kbit/s)
Time Slot 0
t6
The four Multiplex Configuration Registers are at zero (no delay).
tx t1 t2 t3 t4 t4GCI t5 t6
Parameter Clock Period if 4096 kHz (3072) Clock Period if 8192 kHz (6144) Delay between Clock A and Clock B Set up time Frame A/CLOCK A Hold time Frame A (or B)/CLOCK A (or B) Duration of Frame A (or B) Clock ratio t5h/t5l Duration of FSCG
T min. 239 (320) 120 (158) - 60 10 10 10 75%
T typ 244 (325) 122 (162) 0
T max 249 (330) 125 (165) +60 t1-10 t1-10 125000-(t1-10)
Unit ns ns ns ns ns ns % ns
100% 488 (650)
125%
106/130
STLC5466
2.2 TDM synchronization
Figure 2-2: Sychronization signals received by the Multi-HDLC
CLOCK A (or B)
t2
DCLK delivered by the Multi-HDLC
t1
t3
FS received by the Multi-HDLC
t4
t5 t6
Bit7, Time Slot 31 Bit0, Time Slot 0
DOUT 0/7, CB
t7 t7
DIN 0/8
t9 t8
Echo
The four Multiplex Configuration Registers are at zero (no delay between FS and Multiplexes).
Parameter t1 t2 t3 t4 t5 t6 t7 t7 t8 t9 DCLK Clock Period if 4096 kHz (3072) DCLK Clock Period if 2048 kHz (1536) Delay between CLOCK A or B and DCLK (30pF) Set up time FS/DCLK Hold time FS/DCLK Duration FS DCLK to data 50 pF DCLK to data 100 pF Set up time data/DCLK Hold time data/DCLK Set up Echo/DCLK (rising edge) Hold time Echo/DCLK (rising edge)
T min Id CLOCKA or B (T min)
T typ 244 (325) 488 (651) 5
T max Id CLOCKA or B (T max) 30 t1-20
Unit ns ns ns ns ns
20 20 244 (325)
125000-244 50 100
ns ns ns ns ns
20 20 155 205
ns ns
107/130
STLC5466
2.3 GCI interface
Figure 2-3: Sychronization signals delivered by the Multi-HDLC
125ms FS received by the Multi-HDLC CH 0 DIN4/5 DOUT4/5 CH 1 CH7
B1
B2
MON
D
C/I AE
t1
DCLK delivered by the Multi-HDLC
t3
FSCG delivered by the Multi-HDLC
t3
t6
DOUT 0/7, CB If FSCG connected to FS
Bit0,
Time Slot 0
t7 t7
DIN 0/8
The four Multiplex Configuration Registers are at zero (no delay between FS and Multiplexes).
Parameter t1 t3 t5 t6 DCLK Clock Period if 4096 kHz (3072) DCLK Clock Period if 2048 kHz (1536) DCLK to FSCG Duration FS DCLK to data 50 pF DCLK to data 100 pF Set up time data/DCLK Hold time data/DCLK
T min Id CLOCKA or B (T min)
T typical 244 (325) 488 (651)
T max Id CLOCKA or B (T max) 20
244
125000-244 50 100
t7 t7
20 20
108/130
STLC5466
2.4 V* interface
Figure 2-4: V* Synchronisation signal delivered by the Multi-HDLC
125ms FS received by the Multi-HDLC CH 0 DIN4/5 DOUT4/5 CH 1 CH7
B1
B2
MON
D
C/I AT
t1
DCLK delivered by the Multi-HDLC
t3
FSCV* delivered by the Multi-HDLC
t3
DOUT 0/7, CB If FSCG is connected to FS Bit3, Time Slot 31
t7 t7
DIN 0/8
The four Multiplex Configuration Registers are at zero (no delay between FS and Multiplexes)
Parameter t1 t3 t5 t6 Clock Period 4096 kHz DCLK to FSCV* Duration FSCV* Clock to data 50 pF Clock to data 100 pF Set up time data/DCLK Hold time data/DCLK Parameter
T min
T typical 244
T max
20 244 50 100 20 20 T min T typical T max
t7 t7
109/130
STLC5466
3 SDRAM MEMORY TIMING
Figure 3-1: Signals exchanged between SDRAM controller and SDRAM
Signals provided by the Multi-HDLC and received from the Synchronous Dynamic Memory T MCLK is an input. Clock provided by an external clock generation ts th 2.0 1.4 0.8
Input: Data from SDRAM Output: signals to SDRAM
2.0 1.4 0.8 td
Parameter T ts th td 1/T= 33, 50 or 66 MHz Data in set up time Data in Hold time Delay between rising edge of CLK and each signal delivered by the Multi-HDLC CL= 5 pF (Vdd = 3.3V 5% Temp 0 to 70C) CL= 30 pF CL= 50 pF
T min
T max
Unit
3 2
ns ns
3 3 3
10 12 20
ns ns ns
110/130
STLC5466
4 4.1 MICROPROCESSOR TIMING ST9 family; MOD0 = 1, MOD1 = 0, MOD2 = 0
Figure 4-1: ST9 read cycle
NCS0/1 t1 NDSACK1 / READY NAS / ALE NDS / NRD t4 t12 t11 t5
A0/7
t2
t3
t6
t7
D0/7
t8
AD0/7 t9
t10 R/W / NWR
tx t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12
Parameter Delay ready /Chip Select (if t3 >t1), (30 pF) Delay when immediate access Hold time Chip Select /Data Strobe Delay ready /NAS (if t1 >t3), (30 pF) Delay when immediate access Width NAS Set up time Address /NAS Hold time Address /NAS Data valid before ready Data bus at high impedance after Data Strobe (30 pF) Set up time R/W /NAS Hold time R/W /Data Strobe Width NDS when immediate access Delay NDS / NCS
T min 0
T max 98
Unit ns ns ns
14 0 98 20 9 9 0 0 15 15 50 5 15
ns ns ns ns ns ns ns ns ns ns ns
111/130
STLC5466
Figure 4-2: ST9 write cycle
NCS0/1 t1 NDSACK1/ READY NAS/ ALE NDS/ NRD t4 t12 t11 t5 t6 t7
D0/7
t2
t3
t8
AD0/7 t9 R/W / NWR
A0/7
t10
tx t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12
Parameter Delay ready /Chip Select (if t3 >t1), (30 pF) Delay when immediate access Hold time Chip Select /Data Strobe Delay ready /NAS (if t1 >t3), (30 pF) Delay when immediate access Width NAS Set up time Address /NAS Hold time Address /NAS Set up time Data /Data Strobe Hold time Data /Data Strobe Set up time R/W /NAS Hold time R/W /Data Strobe Width NDS when immediate access Delay NDS / NCS
T min 0
T max 98
Unit ns ns ns
14 0 98 20 9 9 -15 15 15 15 50 5
ns ns ns ns ns ns ns ns ns ns ns
112/130
STLC5466
4.2 ST10/C16x mult. A/D; MOD0 = 1, MOD1 = 0, MOD2 = 1
Figure 4-3: ST10 (C16x) read cycle; multiplexed A/D
NCS0/1 t2 NDSACK0 / NDTACK / NREADY NAS / ALE NDS / NRD t5 AD0/15 R/W / NWR NBHE A16/23 t6 t4 t12 t7 t8 t1 t3
A0/15
D0/15
t9
t10
tx t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t12
Parameter Delay NOT READY /NRD (if NCS0/1=0), (30 pF) Delay when immediate access Hold time Chip Select / NRD Delay NOT READY / NRD rising edge Delay when immediate access Width ALE Set up time Address /ALE Hold time Address /ALE Data valid before ready Data bus at high impedance after NRD (30 pF) Set up time NBHE, AddressA16/23 /ALE Hold time NBHE / NRD Delay NRD / NCS
T min 0
T max 98
Unit ns ns ns
10 0 98 20 5 5 0 0 5 10 0 15
ns ns ns ns ns ns ns ns ns ns
113/130
STLC5466
Figure 4-4: ST10 (C16x) write cycle; multiplexed A/D
NCS0/1 t2 NDSACK0/ NDTACK / NREADY t4 NAS / ALE NDS / NRD t12 t5
A0/15
t1 t3
t6
D0/15
t8
AD0/15 R/W / NWR t9 NBHE A16/23
t7 t10
tx t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t12
Parameter Delay NOT READY /ALE (if NCS0/1=0), (30 pF) Delay when immediate access Hold time Chip Select / NWR Delay NOT READY / NWR rising edge Delay when immediate access Width ALE Set up time Address /ALE Hold time Address /ALE Set up time Data /NWR Hold time Data /NWR Set up time NBHE-AddressA16/23 /ALE Hold time NBHE-/NWR Delay NWR / NCS
T min 0
T max 98
Unit ns ns ns
10 0 98 20 5 5 -15 15 5 10 0
ns ns ns ns ns ns ns ns ns ns
114/130
STLC5466
4.3 ST10/C16x demult. A/D; MOD0 = 0, MOD1 = 1, MOD2 = 1
Figure 4-5: ST10 (C16x) read cycle; demultiplexed A/D
NCS0/1 t2 NDSACK0 / DTACK / NREADY NAS / ALE NDS / NRD t7 D0/15 R/W / NWR A0/15 / AD0/15 A16/23 NBHE t8 t4 t12 t1 t3
t9
t10
tx t1 t2 t3 t4 t7 t8 t9 t10 t12
Parameter Delay NOT READY / NRD (if NCS0/1=0), (30 pF) Delay when immediate access Hold time Chip Select / NRD Delay NOT READY / NRD rising edge Delay when immediate access Width ALE Data valid before NOTREADY falling edge (30 pF) Data bus at high impedance after NRD (30 pF) Set up time NBHE, Address AD0/15, A16/ /ALE Hold time NBHE, Address AD0/15, A16/23 / NRD Delay NRD / NCS
T min 0
T max 98
Unit ns ns ns
10 0 98 20 0 0 5 10 0 15
ns ns ns ns ns ns ns ns
115/130
STLC5466
Figure 4-6: ST10 (C16x) write cycle; demultiplexed A/D
NCS0/1 t2 NDSACK0/ DTACK// NREADY t4 NAS / ALE NDS / NRD t12 t8 D0/15 R/W / NWR t9 A0/15 / AD0/15 A16/23 NBHE t7 t10 t1 t3
tx t1 t2 t3 t4 t7 t8 t9 t10 t12 tx t1
Parameter Delay NOT READY / NWR (if NCS0/1=0), (30 pF) Delay when immediate access Hold time Chip Select / NWR Delay NOT READY / NWR rising edge Delay when immediate access Width ALE Set up time Data /NWR Hold time Data /NWR Set up time NBHE, Address AD0/15, A16/23 /ALE Hold time NBHE, Address AD0/15, A16/23 /NWR Delay NWR / NCS Parameter Delay NOT READY / NWR (if NCS0/1=0), (30 pF) Delay when immediate access
T min 0
T max 98
Unit ns ns ns
10 0 98 20 -15 15 5 10 0 T min 0 T max 30
ns ns ns ns ns ns ns ns Unit ns
116/130
STLC5466
4.4 80C188; MOD0 = 1, MOD1 = 1, MOD2 = 0
Figure 4-7: 80C188 read cycle
NCS0/1 t1 NDSACK1/ READY NAS / ALE NDS / NRD t5 AD0/7 A0/7 t6 t7 t8 D0/7 t4 t2
t3 t12
R/W / NWR
tx t1 t2 t3 t4 t5 t6 t7 t8 t12
Parameter Delay ready /Chip Select (if t3 >t1), (30 pF) Delay when immediate access Hold time Chip Select / NRD Delay ready /ALE (if t1 >t3), (30 pF) Delay when immediate access Width ALE Set up time Address /ALE Hold time Address /ALE Data valid before ready Data bus at high impedance after NRD (30 pF) Delay NDS / NCS
T min 0
T max 98
Unit ns ns ns
10 0 98 20 5 5 0 0 0
ns ns ns ns ns ns ns ns
117/130
STLC5466
Figure 4-8: 80C188 write cycle
NCS0/1 t1 NDSACK1/ READY NAS / ALE NDS / NRD t5 A0/7 t7 t6 D0/7 t4 t3 t2
t12 t8
AD0/7 R/W / NWR
tx t1 t2 t3 t4 t5 t6 t7 t8 t12
Parameter Delay ready /Chip Select (if t3 >t1), (30 pF) Delay when immediate access Hold time Chip Select / NWR Delay ready /ALE (if t1 >t3), (30 pF) Delay when immediate access Width ALE Set up time Address /ALE Hold time Address /ALE Set up time Data /NWR Hold time Data /NWR Delay NWR / NCS
T min 0
T max 98
Unit ns ns ns
10 0 98 20 5 5 -15 15 0
ns ns ns ns ns ns ns ns
118/130
STLC5466
4.5 80C186; MOD0 = 1, MOD1 = 1, MOD2 = 1
Figure 4-9: 80C186 read cycle
NCS0/1 t1 NDSACK1 / READY NAS / ALE NDS / NRD t5 AD0/15 R/W / NWR NBHE A16/19
A0/15
t2
t3 t4 t12
t6
t7
D0/15
t8
t9
NBHE A16/19
t10
NBHE
t11
tx t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12
Parameter Delay ready /Chip Select (if t3 >t1), (30 pF) Delay when immediate access Hold time Chip Select / NRD Delay ready /ALE (if t1 >t3), (30 pF) Delay when immediate access Width ALE Set up time Address /ALE Hold time Address /ALE Data valid before ready Data bus at high impedance after NRD (30 pF) Set up time NBHE-AddressA16/19 /ALE Hold time AddressA1619 /NRD Hold time NBHE- /NRD Delay NRD / NCS
T min 0
T max 98
Unit ns ns ns
10 0 98 20 5 5 0 0 5 10 10 0 15
ns ns ns ns ns ns ns ns ns ns ns
119/130
STLC5466
Figure 4-10: 80C186 write cycle
NCS0/1 t1 NDSACK1/ READY NAS / ALE NDS / NRD t5
A0/15
t2
t4
t3
t12 t6
D0/15
t8
AD0/15 R/W / NWR t9 NBHE A16/19
t7 t10
NBHE A16/19
t11
NBHE
tx t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12
Parameter Delay ready /Chip Select (if t3 >t1), (30 pF) Delay when immediate access Hold time Chip Select / NWR Delay ready /ALE (if t1 >t3), (30 pF) Delay when immediate access Width ALE Set up time Address /ALE Hold time Address /ALE Set up time Data /NWR Hold time Data /NWR Set up time NBHE-AddressA16/19 /ALE Hold time Address16/19/ALE Hold time NBHE-/NWR Delay NWR / NCS
T min 0
T max 98
Unit ns ns ns
10 0 98 20 5 5 -15 15 5 10 10 0
ns ns ns ns ns ns ns ns ns ns ns
120/130
STLC5466
4.6 386EX: MOD0 = 0, MOD1 = 1, MOD2 = 0
Figure 4-11: 386EX read cycle (LBA# at Vdd)
cycle 1 cycle 2
MCLK
ts NDS/NRD/ CLKOUT ts NAS/ ALE th
th
A1/23
A0/NBLE SIZE1/ NBHE /NUDS
ts
1) No wait state case R/W /NWR/ WRNRD NCS0/1/2
ts
th
tdd
tdh
Dout 0/15
ty NDSACK0/ NDTACK/ NRDY tyz
tdz
2) Wait state case R/W /NWR/ WRNRD NCS0/1/2
ts
th
td1
tdh
Dout 0/15
ty NDSACK0/ NDTACK/ NRDY n Twait tyz
tdz
tx ts th tdd tdh tdz ty tyz
Parameter Set up time/MCLK rising edge for CLKOUT, ALE, Addresses, WRNRD, NCS0/2 Hold time / MCLK rising edge for CLKOUT, WRNRD, NCS0/1/2 Data out delay time / MCLK rising edge (50 pF) Data out Hold time / MCLK rising edge (50 pF) Data floating delay / MCLK rising edge Delay NRDY low / MCLK rising edge (50 pF) NRDY Delay floating / MCLK rising edge (50 pF)
min 6 2 4 4 4 4
max
Unit ns ns
20
ns ns
15 20 10
ns ns ns
121/130
STLC5466
Figure 4-12: 386EX write cycle (LBA# at Vdd)
cycle 1 cycle 2
MCLK
ts NDS/NRD/ CLKOUT ts NAS/ ALE th
th
A1/23
A0/NBLE SIZE1/ NBHE /NUDS
ts
1) No wait state case
R/W /NWR/
ts
th
WRNRD
ts th
NCS0/1/2
tds tdh
Stable
Din 0/15
NDSACK0/ NDTACK/ NRDY ty
tyz
2) Wait state case NCS0/1/2
ts
th
tds
tdh
Stable
Din0/15
NDSACK0/ NDTACK/ NRDY
ty
tyz
n Twait
tx ts th tdd tdh tdz ty tyz
Parameter Set up time/MCLK rising edge for CLKOUT, ALE, Addresses, WRNRD, NCS0/2 Hold time / MCLK rising edge for CLKOUT, WRNRD, NCS0/1/2 Data out delay time / MCLK rising edge (50 pF) Data out Hold time / MCLK rising edge (50 pF) Data floating delay / MCLK rising edge Delay NRDY low / MCLK rising edge (50 pF) NRDY Delay floating / MCLK rising edge (50 pF)
min 6 2 4 4 4 4
max
Unit ns ns
20
ns ns
15 20 10
ns ns ns
LBA#, Ready# signals delivered by EX386 and NRDY deliverd by the MHDLC
EX386 R MHDLC
Ready# LBA#
NRDY (pin 59) NLBA (pin 57)
122/130
STLC5466
Figure 4-13: 386EX; NRDY versus LBA#
cycle2 or idle cycle 1 cycle2 cycle2 cycle 1 or idle cycle 2 or idle
MCLK
ts th
CLKOUT
ts
NLBA NRDY 3v delivered by Z MHDLC 0v Ready# 3v delivered by Z EX 386 0v 3v NRDY+Ready# Z seen on the bus 0v
One Twait min
ty
tyz
tx ts th ty tyz
Parameter Set up time/MCLK rising edge for CLKOUT, NLBA Hold time / MCLK rising edge for CLKOUT Delay NRDY low / MCLK rising edge (50 pF) NRDY Delay floating / MCLK rising edge (50 pF)
min 6 2 4 4
max
Unit ns ns
20 10
ns ns
123/130
STLC5466
4.7 68000; MOD0 = 0, MOD1 = 0, MOD2 = 1
Figure 4-14: 68000 read cycle
NCS0/1 t1 NDTACK t3 t2 t4
NAS/ALE
SIZE0/NLDS SIZE1/NUDS A1/23 R/W / NWR
t6 t5 A1/23 t7 t8
D0/15
tx t1 t2 t3 t4 t5 t6 t7 t8
Parameter Delay NDTACK /NCS0/1 (if t3>t1), (30 pF) Delay when immediate access Hold time Chip Select / NLDS-NUDS Delay NDTACK /NLDS-NUDS falling edge (if t1>t3), (30 pF) Delay when immediate access Delay NDTACK /NLDS-NUDS rising edge Set up time Address and R/W / last NLDS-NUDS or NCS Hold time Address and R/W / NLDS-NUDS Data valid before NDTACK falling edge (30 pF) Data bus at high impedance after NLDS-NUDS rising edge (30 pF)
T min 0
T max 98
Unit ns ns ns ns
0 0 98 0 0 0 0 0 15 15 20
ns ns ns ns ns
124/130
STLC5466
Figure 4-15: 68000 write cycle
NCS0/1 t1 NDTACK t3 t2 t4
NAS/ALE
SIZE0/NLDS SIZE1/NUDS A1/23 R/W / NWR
t6 t5 A1/23 t9 t10
D0/15
tx t1 t2 t3 t4 t5 t6 t9 t10
Parameter Delay NDTACK /NCS0/1 (if t3>t1), (30 pF) Delay when immediate access Hold time Chip Select / NLDS-NUDS Delay NDTACK /NLDS-NUDS falling edge (if t1>t3), (30 pF) Delay when immediate access Delay NDTACK /NLDS-NUDS rising edge Set up time Address and R/W/last NLDS-NUDS or NCS Hold time Address /NLDS-NUDS Set up time Data /NLDS-NUDS Hold time Data /NLDS-NUDS
T min 0
T max 98
Unit ns ns ns
0 0 98 20 0 0 0 7
ns ns ns ns ns ns ns
125/130
STLC5466
4.8 68020; MOD0 = 0, MOD1 = 0, MOD2 = 2
Figure 4-16: 68020 read cycle
NCS0/1 t1 NDSACK0/ NDTACK NDSACK1/ READY NAS / ALE t3 t4 t2
NDS /NRD SIZE0/ NLDS SIZE1/ NUDS t5 A 0/23 R/W / NWR t7 t8 t6
D0/15
tx t1 t2 t3 t4 t5 t6 t7 t8
Parameter Delay NDSACK /NCS0/1 (if t3>t1), (30 pF) Delay when immediate access Hold time Chip Select / NDS rising edge Delay NDSACK1 /NDS falling edge (if t1>t3), (30 pF) Delay when immediate access Delay NDSACK1 /NDS rising edge Set up time Address and R/W/last NDS or NCS Hold time Address /NDS Data valid before NDSACK1falling edge (30 pF) Data High Impedance after NDS (30 pF)
T min 0
T max 98
Unit ns ns ns
0 0 98 20 0 0 0 0 15 15
ns ns ns ns ns ns ns
126/130
STLC5466
Figure 4-17: 68020 write cycle
NCS0/1 t1 NDSACK0/ NDTACK NDSACK1/ READY NAS / ALE t3 t4 t2
NDS /NRD SIZE0/ NLDS SIZE1/ NUDS t5 A 0/23 R/W / NWR t9 D0/15 t10
t6
tx t1 t2 t3 t4 t5 t6 t9 t10
Parameter Delay NDTACK /NCS0/1 (if t3>t1), (30 pF) Delay when immediate access Hold time Chip Select / NDS rising edge Delay NDSACK1 /NDS falling edge (if t1>t3), (30 pF) Delay when immediate access Delay NDSACK1 /NDS rising edge Set up time Address and R/W/last NDS or NCS Hold time Address /NDS Set up time Data /NDS Hold time Data /NDS
T min 0
T max 98
Unit ns ns ns
0 0 98 20 0 0 0 7
ns ns ns ns ns ns ns
127/130
STLC5466
5 5.1 MASTERCLOCK and TOKEN RING TIMING Masterclock timing
Figure 5-1: Masterclock
1/f th Masterclock applied to MCLK (pin4) tl
tx f th tl tx f th tl tx f th tl
Parameter Masterclock frequency Masterclock high Masterclock low Parameter Masterclock frequency Masterclock high Masterclock low Parameter Masterclock frequency Masterclock high Masterclock low
T min 30 12 12 T min 60 6 6 T min 45 8 8
T typ 32.768
T max 33.3
Unit MHz ns ns
T typ 65.536
T max 66.6
Unit MHz ns ns
T typ 49.152
T max 50+100p pm
Unit MHz ns ns
128/130
STLC5466
5.2 Token ring timing
Figure 5-2: Token ring
1/f Masterclock applied to MCLK pin a TRO ts th a
TRI
tx f a ts/th
Parameter f: Masterclock frequency Delay between Masterclock rising edge and edges of TRO pulse delivered by the MHDLC (30 pF) This input is sampled in asynchronous mode
T min 32
T max 66 12
Unit MHz ns ns
5
129/130
STLC5466
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. The ST logo is a registered trademark of STMicroelectronics (R) 1999 STMicroelectronics - All Rights Reserved STMicroelectronics GROUP OF COMPANIES Australia - Brazil - China - Finland - France - Germany - Hong Kong - India - Italy - Japan - Malaysia - Malta - Morocco - Singapore - Spain - Sweden - Switzerland - United Kingdom - U.S.A. http://www.st.com
130/130

▲Up To Search▲

Price & Availability of STLC5466

	To Download STLC5466 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .